Hi,
I would like to verify few details in my design which includes MSP430F5438:
1. I'm going to connect SPI pins (e.g. 76,77,78,79) directly to 32 chips with the following parameters:
LOGIC INPUTS (SDI, SCLK, , SDA, GPIO) CS
|
|||||
V IH Input High Voltage |
0.7 × V DRIVE |
V
|
|||
V IL Input Low Voltage |
0.4
|
V
|
|||
I IH Input High Current |
−1
|
μA
|
V IN = VDRIVE |
||
I IL Input Low Current |
1
|
μA
|
V IN = GND |
||
Hysteresis
|
150
|
mV
|
Table 4. SPI Timing Specifications ParameterParameter |
Limit
|
Unit
|
Description
|
f
SCLK |
5
|
MHz max
|
SCLK frequency
|
t
1 |
5
|
ns min
|
falling edge to first SCLK falling edge CS
|
t
2 |
20
|
ns min
|
SCLK high pulse width
|
t
3 |
20
|
ns min
|
SCLK low pulse width
|
t
4 |
15
|
ns min
|
SDI setup time
|
t
5 |
15
|
ns min
|
SDI hold time
|
t
6 |
20
|
ns max
|
SDO access time after SCLK falling edge
|
t
7 |
16
|
ns max
|
rising edge to SDO high impedance CS
|
t
8 |
15
|
ns min
|
SCLK rising edge to high CS
|
Is this OK in terms of load and timing?
2. What is the maximum UART rate in transmission?
Thanks,
Rafi