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MSP432 Timer32 minimal load value.

Good day.

Is there minimal value of the load register of a Timer32?

I see (using a scope), that for 24MHz clock, periodic mode and counter > 100, I toggle an GPIO and everything is OK,

BUT for lower values it goes crazy.

How may I evaluate minimal counter?

Thank you.

  • Hi Alexander,

     In my case I was able to set the counter of 1 without any problems. (@ 24MHz ~ 12us period)

    Here is my timer32 configuration:

    volatile uint32_t timer32Count = 1;
    void configureTimer32(void)
    {
    	MAP_Timer32_initModule(TIMER32_0_MODULE, TIMER32_PRESCALER_1, TIMER32_32BIT,
    			TIMER32_PERIODIC_MODE);
    	MAP_Timer32_setCount(TIMER32_0_MODULE,timer32Count);
    
    	MAP_Interrupt_enableInterrupt(INT_T32_INT1);
        MAP_Timer32_enableInterrupt(TIMER32_0_MODULE);
        MAP_Timer32_startTimer(TIMER32_0_MODULE, true);
    }

    And my ISR:

    void timer32IntHandler(void)
    {
        MAP_Timer32_clearInterruptFlag(TIMER32_0_MODULE);
        MAP_GPIO_toggleOutputOnPin(GPIO_PORT_P1, GPIO_PIN0);
        MAP_Timer32_setCount(TIMER32_0_MODULE,timer32Count);
    }

    Just in case this is my clock configuration:

    void setSystemClock(uint32_t CPU_Frequency)
    {
    	/* Setting the external clock frequency. This API is optional, but will
    	 * come in handy if the user ever wants to use the getMCLK/getACLK/etc
    	 * functions
    	 */
    	MAP_CS_setExternalClockSourceFrequency(32768, CPU_Frequency);
    
    	/* Before we start we have to change VCORE to 1 to support the 48MHz frequency */
    	MAP_PCM_setCoreVoltageLevel(PCM_AM_LDO_VCORE1);
    	MAP_FlashCtl_setWaitState(FLASH_BANK0, 2);
    	MAP_FlashCtl_setWaitState(FLASH_BANK1, 2);
    
    	/* Starting HFXT and LFXT in non-bypass mode without a timeout. */
    	MAP_CS_startHFXT(false);
    	MAP_CS_startLFXT(false);
    
    	/* Initializing the clock source as follows:
    	 *      MCLK = HFXT/2 = 24MHz
    	 *      ACLK = LFXT = 32KHz
    	 *      HSMCLK = HFXT/4 = 12MHz
    	 *      SMCLK = HFXT/2 = 24MHz
    	 *      BCLK  = REFO = 32kHz
    	 */
    	MAP_CS_initClockSignal(CS_MCLK, CS_HFXTCLK_SELECT, CS_CLOCK_DIVIDER_2);
    	MAP_CS_initClockSignal(CS_ACLK, CS_LFXTCLK_SELECT, CS_CLOCK_DIVIDER_1);
    	MAP_CS_initClockSignal(CS_HSMCLK, CS_HFXTCLK_SELECT, CS_CLOCK_DIVIDER_4);
    	MAP_CS_initClockSignal(CS_SMCLK, CS_HFXTCLK_SELECT, CS_CLOCK_DIVIDER_2);
    	MAP_CS_initClockSignal(CS_BCLK, CS_REFOCLK_SELECT, CS_CLOCK_DIVIDER_1);
    }

    Hopefully this helps.

      Regards,

       David

  • Thank you so much, David.

    I will check it at the nearest workday and will reply you more detailed.

    Once more thank you.

  • David, have you tried to get it using internal clock

  • Alexander Goldin said:
    How may I evaluate minimal counter?

    Count the number of CPU clock cycles used to service the ISR. 

    Peter

  • Thank you, Peter.

    We did it ;). Our ISR is very light-weight.

  • Are you sure? The problem really smells like there are not enough CPU cycles to serve every interrupt. Don't forget interrupt latency, save and restore of used registers etc. And maybe other interrupts that may cause additional delays.

    David, 12µs cycle time means 6µs per interrupt call, which is only 166kHz interrupt frequency. No wonder if the code in your ISR are actually function calls and not macros.
    But I might have missed something here, I'm not familiar with the Timer32.

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