MSP430g2553 problem with the UCB0 in I2C mode

Hi Everton,

Without knowing what data you are sending the slave device, I cannot tell if this is an issue with our device or on the slave side. If using a different master worked correctly, the issue might be in the initialization code for the msp device. Please provide more information to help solve this problem.

Regards,
Michael Arriete

Everton Reis said:

But, the line SCL change when the SDA line change!!? Why? This is not alowed by I2c protocol!

I think you have misread the I2C-bus specification. When SCL is Low SDA may change, when SCL is High SDA must be stable and is valid.

On your picture you are transmitting to address 10h, but there is no Slave Acknowledging the transmission.

Hi Friend. Here is the code.
I'm sending the data 0x90 (the slave adress) and 0x40 (the control byte). Thank you.
#include <msp430.h>

//const unsigned char Sine_Tab[] = // 16 Point 16-bit Sine Table
//{
// 0,
//};

int main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop Watchdog Timer
P1SEL |= BIT6 + BIT7; // Assign I2C pins to USCI_B0
P1SEL2|= BIT6 + BIT7; // Assign I2C pins to USCI_B0
UCB0CTL1 |= UCSWRST; // Enable SW reset
UCB0CTL0 = UCMST + UCMODE_3 + UCSYNC; // I2C Master, synchronous mode
UCB0CTL1 = UCSSEL_2 + UCSWRST; // Use SMCLK, keep SW reset
UCB0BR0 = 255; // fSCL = SMCLK/12 = ~100kHz
UCB0BR1 = 255;
UCB0I2CSA = 0x90; // Set slave address
UCB0CTL1 &= ~UCSWRST; // Clear SW reset, resume operation
//IE2 |= UCB0TXIE; // Enable TX ready interrupt
UCB0CTL1 |= UCTR + UCTXSTT; // I2C TX, start condition

do
{
__delay_cycles(100000);
UCB0CTL1 |= UCTR + UCTXSTT;
UCB0TXBUF = 0x040;
}
while (UCB0STAT & UCNACKIFG);

UCB0TXBUF = 0x040; // Write DAC control byte
IE2 |= UCB0TXIE;
__bis_SR_register(GIE);//CPUOFF + // Enter LPM0 w/ interrupts
while(1);
}

Slave address 90h doesn’t exist (in this mode), max is 77h. Address 90h will be altered to 10h, as you can see on your picture.

Ok. But the slave address is 0x90 > 0x77. What I do to transmite the MSB bit that is one ( >1< 001 0000 = 0x90)?

The I2C address is only 7-bit (7:1), bit-0 is the R/W-bit.

Sorry, The slave adress is 0x48 < 0x77 and the R/W bit is zero. Thus, the first data after the start bit is 0x48 = >0100 1000< + the R/W bit >0<, we have to send 100 1000 >0< (R/W) = 1001 0000 = 0x90 = 0x48|0. And why, it doesn't work.

Ok, now we comes to the point.
The UCSI inserts automatically the R/W-bit controlled by the UCTR bit, so don’t shift the address just write the ‘real’ address to the UCBxI2CSA register.

Everton,

Did our most recent suggestion solve your issue?

Regards,
Michael Arriete

Thank you Michael. All ok. It's right. UCTR is the bit R/W.

Glad we could help get this issue settled for you!

Regards,
Michael Arriete