I have a code that generates a PWM. Can someone tell me how to add code to the existing to generate a PWM and give it a delay to certain amount and get that out through one of the ports?
Hi Yashaswy!
Here is some code for you that does the following: The first PWM is on P1.4 (TB0.1) and has a duty-cycle of 16ms. The second PWM on P1.3 (TA1.2) starts 12ms later and also has a duty-cycle of 16ms. Both have a period of 50ms.
Connect your probes here:
#include <msp430fr5969.h>
#define PERIOD 50000 // 50ms @ SMCLK = 1MHz
#define DUTY_CYCLE 16000 // 16ms @ SMCLK = 1MHz
#define DELAY 12000 // 12ms @ SMCLK = 1MHz
void main( void )
{
WDTCTL = WDTPW | WDTHOLD; // Stop watchdog timer
P1SEL0 = 0x08 | 0x10; // Enable timer function for P1.3 (TA1.2) and P1.4 (TB0.1)
P1DIR = 0x08 | 0x10; // Set P1.3 (TA1.2) and P1.4 (TB0.1) to output direction
PM5CTL0 &= ~LOCKLPM5; // Disable GPIO power-on default high-impedance mode
CSCTL0_H = CSKEY >> 8; // Unlock CS registers
CSCTL1 = DCOFSEL_6; // Set DCO = 8MHz
CSCTL2 = SELA__VLOCLK | SELS__DCOCLK | SELM__DCOCLK; // Set ACLK = VLOCLK, SMCLK = MCLK = DCOCLK
CSCTL3 = DIVS__8 | DIVM__8; // Set SMCLK and MCLK divider to 8 -> 1MHz
CSCTL0_H = 0; // Lock CS registers
TB0CCR0 = PERIOD - 1; // Period for 1st PWM
TB0CCR1 = DUTY_CYCLE; // Duty cycle for 1st PWM
TB0CCR2 = DELAY; // Delay to start 2nd PWM
TB0CCTL1 = OUTMOD_7; // TB0.1 reset/set mode (P1.4)
TB0CCTL2 = CCIE; // Compare interrupt for 12ms delay
TA1CCR0 = PERIOD - 1; // Period for 2nd PWM
TA1CCR2 = DUTY_CYCLE; // Duty cycle for 2nd PWM
TA1CCTL2 = OUTMOD_7; // TA1.2 reset/set mode (P1.3)
TB0CTL = TBSSEL_2 | ID_0 | MC_1 | TBCLR; // 1st PWM: SMCLK, divider 1, up-mode, clear
__bis_SR_register( GIE ); // Enable interrupts
while( 1 ); // Endless loop
}
#pragma vector = TIMER0_B1_VECTOR
__interrupt void TIMER0_B1_ISR( void )
{
TA1CTL = TASSEL_2 | ID_0 | MC_1 | TACLR; // 2nd PWM: SMCLK, divider 1, up-mode, clear
TB0CCTL2 = 0x00; // Clear compare interrupt - executed only once
}
P1.4 (TB0.1) is the purple line, P1.3 (TA1.2) is the blue one:
Have fun!
Dennis
Thank you so much Dennis, this is working and I'm getting the respective pulses.
Another thing struck me. The pulse from P1.4 (yellow) and the pulse from P1.2 (green) are not starting at the same time - I mean, both of them have the same Duty cycle but have a phase shift. Is there a way to correct that and get the pulses start at the same time?
Regards,
Yashaswy
Yashaswy Akella said:Can we get the output out of some other port like P1.3 by defining a statement like 'Output from P1.0 must go to P1.3 '
No. Not when using hardware PWM. You can change the output to pins that support the same timer function. For example TB0.1 is available at P2.6 and P1.4, same for other timer outputs. But you cannot choose completely free where to output the signal.
But if you would do it like mentiod here...
Dennis Eichmann said:Use TB0.0 as timebase and TB0.1, 0.2 and 0.3 as duty-cycle for three PWMs with OUTMOD_7. Then use TB0.4 with CCIE and set the CCR register to the delay time you want. Inside the ISR disable the CCIE for TB0.4 and start another timer like TA1 with TA1.0 as timebase and TA1.1 as PWM with OUTMOD_7.
...then all outputs are easy accessible:
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