MSP430FR2355: FRAM write cycle durability and ECC

Hello,

Ryo Akashi said:

1. Read and write endurance

    Customer plan to read and write about 200 byte data every one second.

    If they will use 15 years, the number of read and write will be;

    200(byte) x 60(seconds) x 60(miniutes) x 24(hours) x 365(days) x15(years) ~= 9.46 x 10^10

    Read and write endurance is 10^15(min), so can we judge the eudurance of FRAM is enough for this use case?

The FRAM endurance of 10^15 is based on the bit-cell operations. For your application, the 200 bytes will be spread over multiple FRAM bit-cells, so your estimate should not be multiplied by 200. This equals ~473,040,000 cycles which is much less than 10^15. This assumes you won't be using any type of wear leveling algorithms which would reduce your number of cycles per bit-cell, but I don't think that's necessary here.

For more information about FRAM, you can reference the following resources.

MSP430 FRAM Quality and Reliability

MSP430 FRAM Technology – How To and Best Practices

FRAM FAQs

Ryo Akashi said:

2. FRAM ECC

    When FRAM detect UBDIFG, what should we do?

    There is nothing to do because it may be program area?

    Also, when FRAM detect correctable bit, what kind of action do we need to do? 

　Is it an automatic correction?

The FRAM supports bit error correction and uncorrectable bit error detection. The FRAM uncorrectable bit error flag (UBDIFG) is set if an uncorrectable bit error has been detected in the FRAM error detection logic. The FRAM correctable bit error flag (CBDIFG) is set if a correctable bit error has been detected and corrected. UBDRSTEN enables a power-up clear (PUC) reset if an uncorrectable bit error is detected, and UBDIE enables a NMI event if an uncorrectable bit error is detected. CBDIE enables an NMI if a marginal correctable bit error is detected and corrected.

Regards,

James