Having a great deal of trouble with the 430 (msp430fr5968). Initialize micro and uart (see init code below). Then send a character to the tx buffer (UCA1TXBUF = 0X55;). The transmit data line was high after init but when the character is loaded in the tx buf, txdata goes low and remains there.
I am stumped! It’s like the clock to the uart is not there. This might be two problems.
Checked clock frequency using a timer interrupt for 4,000 clocks (4 MHz ceramic resonator which is running and on frequency connected to HFXT pins) (one millisecond interrupt) and the time for the interrupt is only about 750 us (??).
I’ve got to be doing something really dumb but I can’t find it – so any and all help will be greatly appreciated!!!
Bob Scott
214.673.1439
Init below –
void init_micro(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT interrupt
PMMCTL0 = 0XA540; //UNLOCK PMM REGS
PM5CTL0 = ~LOCKLPM5; //turn on io port config ability
UCA1CTLW0 = 0X00E1; // hold in reset to setup
UCA1BRW = 0x0004; // 57,600 based on 4 MHz clock
UCA1MCTLW = 0x5551; // 57,600 based on 4 MHz clock
// init main registors do port selection first for hfxtl
FRCTL0 = 0xA501; //setwrite protect for FR memory
// init io ports
P1SEL0 = 0x03; // P1.0 & 1 are analog vref
P1SEL1 = 0x03;
P1DIR = 0x80 ; //**++ for testing only, P1 bit 1 is an output for time testing
P1IES = 0x30; // initial interrupts enabled pulser enable this later
P1OUT = 0x00; // initial output state all low
P1IFG = 0; //TRYING TO CLEAR INT FLAGS
P1IE = 0x30;
// Set up port 2
P2SEL0 = 0x00; // all pins are I/O change for bit 7 use compair
P1SEL1 = 0x60; //uart on 5 & 6
P2DIR = 0xBF; // all outputs except RXD
P2IE = 0x00; // interrupts disabled
P2OUT = 0x6F; // initial output state LED's off (high)
// Set up port 3
P3SEL0 = 0x00; // use uart 0 (P3-4,5) other half I/O
P3SEL1 = 0x0C; // comparator c14 - c15
P3DIR = 0xF3; // all outputs except
P3OUT = 0x00; // initial output state all low (RS485 RX)
// Set up port 4
P4SEL0 = 0x00; // all pins are I/O
P4SEL1 = 0x00;
P4DIR = 0xF0; // lower half inputs, upper half outputs
P4OUT = 0x00; // initial output state all low
// Set up port J
PJSEL0 = 0xCF; // BITS 4 & 5 ARE IO are I/O
PJSEL1 = 0x00;
PJDIR = 0x00; // all outputs (not used)
PJOUT = 0x00; // initial output state all low
//CLOCK
CSCTL0 = 0xA500; //set password to change clock registers
CSCTL4 = 0xC009; //HF ON, HIGH DRIVE, OTHE OSCS OFF
CSCTL2 = 0x0055; //HF USED FOR ALL CLOCKS
CSCTL3 = 0x0000; //DIV BY 1 ON ALL CLOCKS
int m = 0; //wait for clock to stabilize
while (m < 1000)
{
m++;
}
CSCTL5 &= ~HFXTOFFG; // RESET FAULTS
// init uarts RS485
UCA1CTLW0 = 0X00E0; // Initialize USART0 state machine (~SWRST) release reset
UCA1IE = UCRXIE; // Enable usart RX interrupt (ONLY rx)
// init timers
TA0CTL = 0x0212; //0x01D6; // SMCLK, count up to TACCR0 (CCR0), clear timer, enable interrupt
TA0CCTL0 = 0x0010; //enable compare int
TA0CCR0 = 0x0F9E; // 1 msec interrupt
TA0CCTL1 = 0;
TA0CCTL2 = 0;
TA0R = 0x0001 ; // start timer
//++ Set up comparator
CECTL0 = 0x008F; // + input ch 15 and - input VREF
CECTL1 = 0x050c ; //++ comp on, normal mode, output filtered, falling edge int
CECTL2 = 0x20D0 ; //++ vfref to - term, 1.2 v ref, ref shared
CEINT = 0x0100 ; // int on
}
