Msp430 von neumann or harvard

The MSP430 is a Von-Neumann architecture.

then how does pipelining implemented

For my reference, what document are you looking at as it relates to pipelining?

I didn't read that pipelining is implemented. This is my assumption that pipeling would be implemented as in new MCU's & by some post describing abt pipeling not abt how this is implemented.

I am not aware of pipelining being impossible to implement in a Von Neumann architecture. It can make it sometimes more difficult, but not impossible. And of course many of the bottlenecks of VN + pipeline are solved by using cache memories.

BrandonAzbell said:

For the record, the MSP430 does not implement pipelining.

The MSP does not, of course, read several instructions while going through the different stages of the previous ones. But this has nothing to do with Von-Neumann or Harvard structure. This kind of pipelining rather depends on the existence of a fixed-length single-word instruction design (like the 32bit instruction word of the Sparc).
Also, the x86 definitely is a Von-Neumann architecture, but from Pentium on, it supports its own kind of pipelining (combined with out-of-order execution, branch prediction and many other things).

But you're right, the different TI docs never explicitely mention this. And due to this lack of information, many people fall into the LPM debugger pit (a breakpoint set after an LPM entry is triggered before LPM is entered)

That's more instruction prefetch than instruction pipelining (which may include prefetch) though, no?

Tony

TonyKao said:

That's more instruction prefetch than instruction pipelining

However, the term 'pipelining' can have a wide variety of meanings. And there are always people who say "if it doesn't go so far as my pipelining implementation, then it isn't pipelining at all by my own definition".
Like the dreaded RISC/CISC dicussion, and, and, and... :(

What are advantages of von neumann over harvard

Aamir Ali said:

What are advantages of von neumann over harvard

Harvard uses a separate memory and address bus for data and code. It allows fetching the next isntruction from code memory while fetching the data from ram for the previous instruciton (if multi-level pipelining is used), and allows to have 64k ram and 64k rom while only using 16 bit addresses. However, accessign constants in ROM requires different assembly instructions than using data from ram. This makes things liek printf (which just gets a pointer, not knowing whether it measn data or code memory) a pain.
The ATMega even has 128k code memory because code memory is word-addressed. Accessing constant byte arrays in this cod ememory is a pain too.

von-Neumann only ha sone address range. Code, data, makes no difference. Code can execute form ram and data can be taken from rom. However, you cannto access code and data simultaneously, as there is only one memory bus. And both, code and data, have to fit into the same address range, requiring more than 16 bit if code+data+peripherals exceed 64k.

Is there any specific reason why TI has selected MSP430 to be von neumann or reason is what mentioned above by you.

If code can be executed from RAm & data from ROM, then why MSP datasheet has separately mentioned Ram =512 bytes & flash =16K?????

Shouldn't it be like total memory is 16K or something like that

any help abt dis

Aamir Ali said:

Is there any specific reason why TI has selected MSP430 to be von neumann or reason is what mentioned above by you.

You are requesting help on this question?  How is this important?  The architecture implementation was chosen 20 years ago.

Aamir Ali said:

If code can be executed from RAm & data from ROM, then why MSP datasheet has separately mentioned Ram =512 bytes & flash =16K?????

Shouldn't it be like total memory is 16K or something like that

Regardless of architecture, specifying how much Flash and RAM is a typical question that is requested, therefore this is why the datasheet is specified the way it is.

BrandonAzbell said:

You are requesting help on this question?  How is this important?  The architecture implementation was chosen 20 years ago.

 

Asking why one architecture is preferred over other.  I think that could be base for those who design MCU  & manufacture from its base.

And you are asking why this is important, even if it was done 20 or 50 years ago. 

Main thing if Someone is working on some MCU one should know  what,why exactly it have

Aamir Ali said:

If code can be executed from RAm & data from ROM, then why MSP datasheet has separately mentioned Ram =512 bytes & flash =16K

If you have a small algorithm that requires to acquire and process large amounts of data (e.g. a realtime signal analyzer), you don't need much flash but much ram. If you have a large program with many constant tables, but only a few variables (e.g. a translator that has large dictionaries but only needs to dynamically store the current user input of a few chars), then you'll need much flash and only small ram.
A good example is the 16xx family. There are devices with 48k flash and 10k Ram, and also those with 60k flash and only 2k ram, even though the rest is 100% identical. If you really neeed to store more than 48k of presistent data but can live with only 2k storage for dynamic data, then use the second, else use the first.

Aamir Ali said:

Asking why one architecture is preferred over other.  I think that could be base for those who design MCU 

But this is not a forum for discussing concepts of processor architecture & design; this is the MSP430 forum - for discussions about using that product.

If you want to study processor architecture & design, there are plenty of books & courses on that subject...

Aamir Ali said:

I read that msp is von -neumann based, then how can pipelining be implemented. As its not possible in VN.

Howeve,r the MSP pipelining only uses one stage: instruction prefetch. And only if the previous instruction doesn't need to write back a result to memory.

However, the Harvard-designed sparc, while having a three-step pipeline, required one step for instruction decoding. Which the MSP does 'instantly'. So if removing this step form the 'pipeline' not much is left over the MSP :) And the MSp does not have this dreaded 'delay slot' or the inability to load a register with an immediate value in one step (the sparc required two, because the value was part of the instruciton and therefore limited in bit-length).
I miss the rotating register set, but that's not depending on harvard or von-neumann at all.

Aamir Ali said:

If code can be executed from RAm & data from ROM, then why MSP datasheet has separately mentioned Ram =512 bytes & flash =16K?????

They are treated as the same; in fact the entire 16-bit range is treated as a single memory space, except certain byte-accessed peripheral registers. However to programmers they are different memory blocks because, well, they are different, in that one is cheap and slow and the other is fast and expensive (even though to the MSP430 microarchitecture there's no difference).

The ARM cores before ARM9 (for example the classic ARM7TDMI) were all von Neumann and had separate RAM and Flash, so I'm not sure why you're so surprised. Surely that's one of the canonical von Neumann processors you've encountered?

Also many processors nowadays are of the "modified Harvard" type, where the internal memory organization is based on Harvard, but the external interface appears as von Neumann to the programmer.

Tony

it was a very good discussion...thnx guys