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Transients on the ADC10 input signal

Other Parts Discussed in Thread: MSP430G2332, MSP430F2272

Hi

With ADC10 in MSP430G2332,
the user guide "ADC10 Inputs and Multiplexer" section mentions
"The ADC10 uses the charge redistribution method. When the inputs are internally switched, the switching
action may cause transients on the input signal. These transients decay and settle before causing errant
conversion"

What could be the voltage level of these "transients".
And can these transients be ignored if there is enough or longer Sample Timing "tsample".

Regards.
Paddu

  • As far as I can tell, this is a case of unlucky phrasing.

    The transients are not a consequence of using charge distribution, but of the fact that the ADC uses a sample&hold mechanism (in opposition to the compare input of a delta-sigma converter).
    The sampling capacitor will most likely have a different voltage than the input signal when the multiplexer connects the two. It may be 0V or reference or perhaps anything in between. The transients are whatever will happen if a charged or discharged capacitor of a few pF is connected to your signal through a 1k resistor (the impedance of the multiplexer) and starts being chaged/discharged to your signal level.

    So it is nothing more than teh expected effect when you charge a smapling capacitor. It just sounds more severe than it is. If tsample is long enough, things are well.

  • Hi Jens-Michael

    Thank you so much.

    As you say "It may be 0V or reference or perhaps anything in between"
    is there any possiblity that the voltage level of these "transients" are upto VCC?

    Actually the Tsample forumula mentioned in the user guide doesn't have any
    realtion with the "transients".
    Tsample > (Rs+Rl)×ln(2^11)×Cl

    Regarding the RS (External source resistance),
    in our application with the external switch the RS value for the Capacitance-charging is
    different from Capacitance-discharging.
    i.e. RS value during Capacitance-charging is lesser than RS value during Capacitance-discharging.

    And the user guide mentions
    "The capacitor CI voltage VC must be charged to within ½ LSB of the source voltage VS for an
    accurate 10-bit conversion"
    So, in this case we may have to calculate the Tsample with regards to the RS value during Capacitance-charging.

    If the "transient" is smaller, we can calculate the Tsample
    with respect to the RS value during Capacitance-charging,
    but if there is a possiblity of the "transient" level upto VCC
    then we need to calculate the Tsample with respect to the RS value during Capacitance-discharging.

    So in order to calculate the sufficient Tsample we may need to know the
    maximum voltage level of the "transients".

    Regards,
    Paddu

  • paddu1 said:
    is there any possiblity that the voltage level of these "transients" are upto VCC?

    Depends on the input and the used reference,. If you use VCC as reference, maybe. or if your input signal is as large.

    paddu1 said:
    Actually the Tsample forumula mentioned in the user guide doesn't have any realtion with the "transients".

    No. This formula calculates the required time to let the capacitor charge or discharge for a certain percentage of the difference between its initial value and the signal voltage. So the absolute voltages are not part of the calculation.

    Teh transients, however, depend on teh difference of the current capacitor voltage and the signal voltage. If e.g. the capacitor is discharged, and the signal is 2.5V, this will result in an instantaneous current of (2.5V-0V)/1k = 2.5mA Due to the small capacitance, this will be for nanoseconds only (or less, I didn't calculate the decay function). However, this is simply what you have to expect when you charge a capacitor. elementary analog electronics.
    If the signal source cannot stand this current, its voltage will break down shortly (which will also reduce the current, and therefore reduce the breakdown etc.). This is the 'transient' you observe.

    paddu1 said:
    i.e. RS value during Capacitance-charging is lesser than RS value during Capacitance-discharging.

    So yur signal source can source but not sink? YOu may want to 'equalize' this by applying a constant load. Voltage regulators have similar problems and require a minimum load to properly work.

    paddu1 said:
    And the user guide mentions
    "The capacitor CI voltage VC must be charged to within ½ LSB of the source voltage VS for an
    accurate 10-bit conversion"
    So, in this case we may have to calculate the Tsample with regards to the RS value during Capacitance-charging.

    Thsi simply means you need to give the capacitor enough time to charge to 1-1/2048 = 99.95% for a 10 bit result. How much tiem it is can be calculated with the formula. A simple constant-voltage capacitor charge calculation. An e-function (as opposed to a constant-current charge, which is linear)

    paddu1 said:
    If the "transient" is smaller,

    Of yocurse it is smaller. The' transient' is the effect of voltage difference. And tsample is calculate to to the point of minimal voltage difference, so the remaining charging current and therefore the current-induced 'transient' is minimal then too.

    paddu1 said:
    So in order to calculate the sufficient Tsample we may need to know the maximum voltage level of the "transients".

    Actually not :) The transients are a side-effect of the charging itself, so if the chaging is complete, the transients are gone.

    Well, in theory, teh voltage drop by the charge current reversely slows down the charge. However, towards end, this results in a faster charge than when tehre was no voltage drop. This counteracts the slowing effect. Thsi has already been taken care for sicne the formula respects the external impedance (and therefor the voltage drop on it by the charge current through it)

    However, I didn't study the charge distribution good enough (I don't know of any TI info regarding the actual implementation) and it can well be that the capacitor is always discharged after a conversion.

    So since you don't know which signal you have  at a given time (else you wouldn't want to sample it), and no authoritative information is availabel about the possible charge state of the capacitor (and what if the conversion was interrupted by software?), I fear you must expect the worst case (discharging).

  • Hello All,

    I have a similar problem in my setup. I am sampling 6 ADC10 inputs of MSP430F2272. Five of the inputs are sampled sequentially at a rate of 1 kHz and the 6th input is sampled at 5 kHz. 

    The signal which is being sampled at 5kHz is an output of a current sensor and is being sampled at a rate of 5kHz  every other 6.5 ms(Not continuous sampling). 

    When this signal is not being sampled, the other five are sampled at 1kHz. 

    The problem is that there exist transients at the ADC10 input being sampled at 5 kHz, when the input signal is zero. The transients range from 200mV to 350mV. And they are only present for the period that input is sampled. Exactly 32 spikes as I take 32 samples. 

    Hopefully I be able to get some information on this issue.

    Thanks,

    Satbir 

     

  • Satbir Sekhon said:
    The problem is that there exist transients at the ADC10 input being sampled at 5 kHz, when the input signal is zero. The transients range from 200mV to 350mV. And they are only present for the period that input is sampled. Exactly 32 spikes as I take 32 samples. 

    When you open the sampling gate for the ADC10, then you connect a 10pF (or 27pF, depends on MSP) discharged capacitor to the input signal through the ~1k switching resistance. This of course causes an instant load on the signal and a scope shot will show a transient (the higher impedance the sourtce is, the higher the transient). During the samplign time, the source will feed the capacitor, which charges, and finally settles at the correct level.
    However, I'm not 100% sure whether the capacitor is really discharged (I don't know the internal workings of the charge distribution ADC). It may as well be that the capacitor is always charged to the reference or to 50% reference and then sources the input. When you switch between channels, it may even be the value of the previous channel. I never checked for this, my own signal sources were always low-impedance enough for this nto being an issue.

  • Thanks Michael,

    I just checked and the output impedance of my current sensor is  125k Ohm (quite high). 

  • Satbir Sekhon said:
    I just checked and the output impedance of my current sensor is  125k Ohm (quite high). 

    Indeed, in relation to the 1k input resistance to teh charge capacitor, this is quite high.
    If your sampling time is long enough, it doesn't matter, though.

    But if you want to use the signal for a different purpose too, what you can do is adding an external capacitor (a few 100pF). It will charge while the ADC is converting or idle and when the ADC samples, most of treh charge is taken from the external capacitor. It adds a low-pass to the signal source, but smoothens the transients. OF yourse you can do an impedance change usign an OpAmp, but this will be overkill in most cases.

  • That was the first thing I did before posting here Michael. I am using 1nF ceramic capacitor, and it does take care of most of the transients. 

    Although it introduces an offset in the ADC reading for that signal,but its not a big problem. 

    I thought, may be I would be able to make some modifications to my code instead of changing the hardware to get rid of the problem.

    Thanks again for fast and insightful responses Michael. 

  • Satbir Sekhon said:
    Although it introduces an offset in the ADC reading for that signal,but its not a big problem. 

    It shouldn't. The cap can only charge to the signal voltage. I don't see where an offset could come from. Of course the additional capacitance forms a low-pass filter with the signal impedance, so if the signal is mostly high, with short low pulses, the low-pass characteristics will attenuate these low pulses which might appear as an offset but actually isn't.

    Satbir Sekhon said:
    I thought, may be I would be able to make some modifications to my code instead

    Since it is a physical problem (not just a hardware problem), there is nothing the software could do.

    As I said, the only way to completely circumvent it is adding an OpAmp as impedance transformer.

    Well there is another thing: adding  a series resistance of 10k or even 100k and greatly increasing sampling time. However, this would limite the maximum sampling frequency. It actually moces teh low-pass from outside the MSp to inside the MSP.

  • The signal is the output of a Current sensor, and the current is being measured through a solenoid, driven by PWM. 

    You are right on the Money about the short low pulses being attenuated by the Low pass characteristic of the CAP setup. I knew that an Op Amp will take care of it for Good, but was looking for an explanation and other possible solutions. 

    And you have covered both !!!

  • Jens-Michael Gross said:
    The cap can only charge to the signal voltage. I don't see where an offset could come from.

    For a 10 bit ADC the external input capacitor should be at least 2000 times  the sampling capacitor. 10nF is a safe value. This way the charge transferred to the input SH cap does not change the voltage on the input cap significantly. 

    Peter

  • Peter Dvorak said:
    For a 10 bit ADC the external input capacitor should be at least 2000 times

    That's correct, but no solution. It would require the delay between two sampling operations equally large.
    The larger the 'smoothing' capacitor is, the longer does the signal source have to work to charge it.
    If the sampling frequency is, say, 10kHz, and the sample time (SHT) is 1µs, then the external capacitor must not be larger than 99 times ((1/(tSHT*fsample))-1) the internal capacitor size or else it will influence the samples.

    So when using both 'requirements', it gives you the maximum sampling frequency in order to get no transients. The low impedance of the external capacitor allows for a short SHT, but the large factor between internal and external capacitor results in a maximum sampling frequency of <500Hz.
    (minimum SHT = 4 ADCOSC cycles, fADCOSC=4MHz, 10 bit-> Ce/Ci = 2048 -> 1MHz/2048 = 488Hz with Ce=Ci*2047)
    For anything beyond, active impedance transformation (OpAmp) is required if no transients are allowed.

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