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Msp430F6736 SD24_B Conversion Rate?

kelly
Prodigy 160 points
Other Parts Discussed in Thread: MSP430F6736

Where I can find the Msp430F6736 SD24_B Conversion Rate? I have found the datasheet and user guide, I got nothing valuable clues. tks very much.

  • 0
    TI__Intellectual 2910 points

    Howdy Kelly,

    Hopefully I can shed some light on this for you.  Sigma Delta converter architecture is a bit different than the SARs most people in the MCU world are used to.  The final sample rate is actually adjustable depending on two key parameters: the peripheral clock, and the over sample rate (OSR).

    In the SD 24 configuration registers you can select which clock you want the ADC to use, and any division you want on that speed.

    The OSR is how many samples per conversion the ADC is using.  A SD ADC uses a long stream of 1-bit samples (collected at the peripheral frequency you set above) that are feed into a filter to come up with the final conversion result.  The OSR is the number of these 1-bit samples that are filtered together.  In general, a higher OSR will yield a more accurate result, but at the expense of requiring longer to convert.  Determining your sample frequency and OSR is heavily dependent on the source signal you'll be processing, so I can't really make any steadfast recommendations.

    Regards,

    Bart Basile

  • 0 in reply to Bart Basile
    Prodigy 140 points

    Bart Basile,

    In the same stream line, I have one query.

    For the same amount of analog input signal provided as input to sigma-delta converter SD24_B in MSP430F6736, what will be effects of changing sampling rate (ratio of modulating frequency to OSR) on converter's output.

    I have observed drastic change on converter's output if i change the sampling rate.

    Is there any calculation for the same that can help in predicting amount of change in converter's output if one changes sampling frequency by some amount?

  • 0 in reply to Bhaskar Thakkar
    Guru 227245 points

    A Delta sigma converter sampling stage is a recoupled difference/integration unit.

    First, the difference (Delta)  between the input signal and either GND or Vref is created (depending on the last conversion result), and the resulting voltage is added (sigma) to the integrator. Then the integrator output is compared to the reference and an output bit is generated from the comparison result.

    This generates a strean of bits, one on each clock pulse.

    If you ignore thedigital filter,. the output bitstream is an exact (in the limits of teh analog precision) representation fo the input signal. The ratio of 0 and 1 bits is exactly the percentage of the reference voltage. If you collect 65536 bits, you#ll get a 16 bit value that is very precise.
    The job of the digital filter is to 'estimate' the total after 65536 bits by looking at the pattern the bits come in. (well, it's a rather rough explanation). Now an OSR of 32 doesn't mean that only 32 bits are used. This is why you have to discard the first few results after an input change or after enabling the ADC.

    It's correc tthat the combination of OSR and clock rate determines the conversion speed and maximum conversion frequency.
    However, the integrator design puts some limits on the minimum and maximum clock frequency. IIRC, the SDs in the MSPs work best with a clock frequency around 1MHz. More is limited by slew rates and such, less affects the integration process. There's a reason why the internal clock is ~1MHz.

  • 0 in reply to Jens-Michael Gross
    TI__Intellectual 2910 points

    Jens,

    The new SD24_B ADCs can sample effectively up to the 2MHz range.

    Bhaskar,

    I would start by looking at your output data format settings; which can change depending on your OSR range.  The exact output expectations in relation to the other settings (like 2's compliment and data alignment) can be found in section 29.2.7.3 of the users guide for this family.

  • 0 in reply to Bart Basile
    Guru 227245 points

    Bart Basile said:
    The new SD24_B ADCs can sample effectively up to the 2MHz range.

    Fine. i don't have a datasheet of a device with SD24_B. However, I expect the device being optimized tfor the defaul tmodule clock (or v.v.)

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