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How to determine if selected MSP430 has shared JTAG pins

Gerry Rues
Prodigy 120 points
Other Parts Discussed in Thread: MSP430F5419A, MSP430F5342

Hi,

Being new to the MPS430 arena I need a basic question answered: “how does one determine if the selected MSP430 chip has shared JTAG pins.”

I see that most all the pins are shared with a general port I/O pin but I do not think that is what is meant by shared pins. I’m trying to enable the BSL on the MSP430F5419A and not sure what pins to connect to. The TI documented pin names do not match the BSL dongle supplier pin names.

The pins on the MSP430F5419A I have selected are:

Pin          Name                                    RS232

91           Test                                       RTS

96           RST                                       DTR       

18           BSL transmit                       RXD

19           BSL receive                         TXD

Can anyone confirm I have selected the correct pins?

And also clarify if the MSP430F5419A has dedicated JTAG pins or not. Per figure 1-2 and 1-3 of the SLA319C manual the RTS line is inverted depending if the MSP430 has shared or dedicated JTAG pins.

Thanks

Gerry

  • 0
    TI__Guru 56650 points

    Hi Gerry,

    basically if the device has TEST pins, it has shared JTAG pin:

    http://processors.wiki.ti.com/index.php/MSP430_FAQ#How_to_invoke_the_BSL.3F

    in MSP430F5419A, i think the JTAG pins are shared with Port J.

  • 0
    Genius 3155 points

    Shared JTAG means simply and exactly shared with other functions, e.g. GPIO or other peripherals.

    MSP430F5419A has a shared JTAG (with port J, that is named after JTAG).

    The pins you have selected seem correct to me, nevertheless you could make a test inserting a series resistor (say 1k) on each line to avoid damages.

    Please note that revisions D, E and G of MSP430F5419A suffer of errata SYS10 (see SLAZ290), I don't know if your BSL dongle supplier is aware of that.

    Regards,

    Peppe

  • 0
    TI__Genius 11255 points

    Hi Gerry,

    If you need more information on the BSL for MSP430, I have provided some links below that may be helpful. Please post if you have any further questions and feel free to create new posts for separate issues.

      

    MSP430F5419A Datasheet (section 1.10 Bootstrap Loader - pg 68):

    http://www.ti.com/lit/pdf/slau208

    MSP430 Memory Programming (including via bootstrap loader):

    http://www.ti.com/lit/pdf/slau265

    MSP430 Programming via the BSL User's Guide (direct link):

    http://www.ti.com/lit/pdf/slau319

    Associated BSL files (from BSL User's Guide above):

    http://www.ti.com/lit/zip/slau319

     

    Thanks,

    Clinton

  • 0
    TI__Genius 11255 points

    Gerry,

    Did you have any further questions on the bootstrap loader? Feel free to post on this thread if you have related questions or start a new thread if you have another issue.

    Thanks,

    Clinton

  • 0 in reply to Clinton Rodgers
    Intellectual 750 points

    Hey there,

    I have a question regarding the use of TEST programming line of MSP430F5342 with JTAG 4-wire.

    My TEST line connects straight from the external programming pin to the MCU (pin 41).

    For the operation of an external charger that connects to my product, I need to add to one of the external pins a pull down resistor (actually a thermistor) that will most likely be around ~10kohm.

    In order to save space and external pins I want to add the pull-down resistor to the TEST line which goes outside of my product anyway.

    I tested it out and it seems to be fine BUT I'm afraid that it may cause damage to my programmer / debugger.

    Does anyone have an idea whether doing such thing is possible or not?

    What would you check if you were me?

    It's really urgent to get to a decision asap so I would appreciate your fast response.

    Thank you very much,

    Nir

  • 0 in reply to Nirke
    Guru 227245 points

    Does the external charger need the pulled-down line for testing the presence of a device? The MSP has an internal pull-down of  ~50k on the TEST pin,. however, the pin should never be pulled high unless you want to init a JTAG session. SO be sure the charger won't pull the pin high actively (e.g. for safe pin state testing)
    An additional pull-down on this pin is no problem as long as it isn't so strong that it prevents JTAG operation by the FET. However, it you plan to use SBW protocol, the SBW signals are very sensitive to timing, and additional pull-downs may influence timing.

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