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MSP430F6726 24 bit sigma-delta ADC question

Rob Mitrunen
Expert 1685 points
Other Parts Discussed in Thread: MSP430F6726, MSP430F6736

I have a question about the 24 bit sigma-delta ADC on the MSP430F6726.

 

I am trying to determine the full range of the ADC, when using the internal reference voltage of 1.151V. According to the datasheet (page 72 - SD24_B, Power Supply and Recommended Operating Conditions):

 

The full-scale range (FSR) is defined by VFS+ = +VREF/GAIN and VFS- = -VREF/GAIN: FSR = VFS+ - VFS- = 2*VREF/GAIN. If VREF is

sourced externally, the analog input range should not exceed 80% of VFS+ or VFS-; i.e., VID = 0.8 VFS- to 0.8 VFS+. If VREF is sourced

internally, the given VID ranges apply. MIN values are calculated based on a VREF of 1.137V (assuming this as the min. value for

internal ref.) TYP values are calculated based on a VREF of 1.151V (assuming this as the typ. value of the internal ref).Values need to be

finalized after characterization based on the final VREF range. All numbers showing input voltage ranges in this document must be

updated with the final numbers for the max. input voltage range. The original starting point for the input voltage range was ±1000mV.

 

The TYP values for a GAIN value of 1 is +-920mV.

 

If we were to set the ADC up to use the top 16 bits of the 24 bit SD ADC, what would the mV per bit resolution?

 

From what I understand, we would have 65536 ADC steps over the Full Scale Range i.e. -1.151 to +1.151 V, right?

 

This would give us a resolution of 0.03512 mV per bit.

 

However, we can only measure up to 80% of Full Scale Range. Is that ‘should’ or ‘can’ only measure 80%?

 

It seems odd to have a 16 bit ADC, but then throw away 20% of our range.

  • 0
    Guru 227245 points

    Rob Mitrunen said:
    However, we can only measure up to 80% of Full Scale Range. Is that ‘should’ or ‘can’ only measure 80%?

    It's a 'should'. Beyond these 80%, the specified performance isn't guaranteed. So if you exceed them, your results are less reliable than below. Still better than a 12 bit ADC, if you use a proper OSR.
    If you learn how a Delta-Sigma internally works, you will see why reference voltage and input range aren't necessarily the same.

    Rob Mitrunen said:
    If we were to set the ADC up to use the top 16 bits of the 24 bit SD ADC, what would the mV per bit resolution?


    Now the whole thing with Delta-Sigma converters is a bit tricky and cannot be compared with SAR-type or FLASH ADCs. 24 bit resolution doesn't mean you can measure a full-range signal with a precision of 0.06ppm. This would be true if you had 100% noiseless amplifiers and othe romponents and an OSR of 16M. However, if the signal is only a fraction of full range, lower bits become significant which were below the noise floor previously. Normally, with OSR1024 you cannot use more than 14 bits down from the highest bit set. Provided that your signal noise isn't larger than that. Or the internal noise due to amplification and other factors.

  • 0 in reply to Jens-Michael Gross
    Expert 1685 points

    The main question I need to have clarified has to do with the Full Scale Range and the ADC resolution, while staying within the 80% measurable range.

     

    In Differential mode, using the internal reference of 1.151 volts, what would be the FSR and the approximate mv/bit resolution.

     

    We have a bit of a difference of opinion going on and we need to clarify this.

     

    I think the following:

    Option 1:

    65536 ADC steps over the Full Scale Range of -1.151 to +1.151 V

     

    This would give us a resolution of 0.03512 mV per bit.

     

    The other proposal is the following:

    Option 2:

    65536 ADC steps over the Full Scale Range of  0 to +1.151 V

     

    This would give us a resolution of 0.017562 mV per bit.

     

    Can you give me a definitive “Option 1” or “Option 2” answer (or an Option 3 if neither is correct!)

  • 0 in reply to Rob Mitrunen
    TI__Genius 10830 points

    What is the objective?  Is it to have the best resolution using the SD24_B?

    What about using the internal reference (SD24REFS = 1) to remove the constraint of using just 80% of the full-scale range (FSR)?

    MSP430x5xx and MSP430x6xx Family User's Guide
    "SD24_B Reference- and Clock Generation Block Diagram"

    It seems that the reference module can be used for the SD24_B.

    MSP430F673x, MSP430F672x Mixed Signal Microcontroller
    "REF Voltage Reference"

    As far as how the ADC counts work, here is an example that demonstrates your options.

    MSP430x5xx and MSP430x6xx Family User's Guide
    "Data Format Example"

    How closely does that match what you are looking for?

  • 0 in reply to Jason Work
    Guru 227245 points

    Jason Work said:
    What about using the internal reference (SD24REFS = 1) to remove the constraint of using just 80% of the full-scale range (FSR)?

    Actually not. Figure 20 shows you the SINAD vs Vpp, normalized to Vref (any Vref).

    Reason for the sudden drop above 88% is the principle how SD24 works. It doesn't doesn't just compare against reference, it integrates the input signal. So the integrator has to cope with twice the reference if the input signal is almost at reference level. Which may even be above VCC if your reference is too large and VCC too small. This greatly affects performance and therefore only a certain percentage of the reference can be used.
    (Note that the performance values are for VCC=3V. If you try the same wiht 1.8V (minimum) voltage, you will get way worse results or have to limit the input to 50% of the reference or less.

    Jason Work said:
    It seems that the reference module can be used for the SD24_B.

    I don't think so. The reference module selectable references are for the ADC10 that is also present in this device. The SD24_B either uses the internal reference of fixed 1.15V (1.137..1.165V) or an external one. However, the internal reference needs to be switched on with SD24REFS bit and requires 200µs settling time for specified performance (100nF capacitor on VREF pin).

  • 0 in reply to Jens-Michael Gross
    TI__Genius 10830 points

    What is the full-scale range of the 24-bit sigma delta analog to digital converter (SD24_B)?

    The full scale range is 2.302 V wthin the bounds of -1 V to 3.0 V (137 nV/ADC count) and the difference between the pair of inputs SDxP0 and SDxN0 cannot exceed Vsd24ref (1.151 V)

    Conditions:

    Device: MSP430F6736
    Voltage reference: (Internal) positive built-in reference voltage of 1.151 V
        SD24REFS = 1
    Supply voltage: 3.0 V
        AVCC = 3.0 V
        DVCC = 3.0 V
        AVSS = 0 V
        DVSS = 0 V
    Programmable gain amplifier set to unit gain
        SD24GAINx = 1

    Absolute input voltage range (VI)
        Min: AVSS - 1V
        Max: AVCC

    This is the lowest and highest voltage that the SD24_B negative and positive analog input pins for the converters can tolerate without risk of damage.  The min and max would be -1.0 V and 3.0 V for these pins:

    SD0P0
    SD0N0
    SD1P0
    SD1N0
    SD2P0
    SD2N0

    Differential full scale input voltage (VID,FS) where VID = VI,A+ - VI,A-
        Min: -VREF/GAIN
        Max: +VREF/GAIN

    This is the maximum voltage difference on a given pair of differential input signals.  In other words, |SDxP0 - SDxN0| <= Vsd24ref of 1.151 V

    In the datasheet's SD24_B, Power Supply and Recommended Operating Conditions there is a note about the full scale range

    SD24_B, Power Supply and Recommended Operating Conditions said:

    The full-scale range (FSR) is defined by VFS+ = +VREF/GAIN and VFS-= -VREF/GAIN: FSR = VFS+ - VFS-= 2*VREF/GAIN.

    For Vsd24ref = 1.151 V and GAIN = 1, then this means the full scale range is FSR = 2*1.151/1 V = 2.302 V.

    In the user's guide find, "Data Format Example for OSR = 256."  In the table, let's examine the row for the format, "Bipolar offset binary,right aligned." and look specficially at how the analog input voltage is recorded.

    0 V analog input voltage is measured when SDxP0 = SDxN0.  It is stored as (hex) 080 0000
    +VFSR is equivalent to VFS+ and is measured when SDxP0 - SDxN0 = Vsd24ref = 1.151 V.  It is stored as (hex) 0FF FFFF
    -VFSR is equivalent to VFS- and is measured when SDxN0 - SDxP0 = Vsd24ref = 1.151 V.  It is stored as (hex) 000 0000

    With a full-scale range of 2*Vsd24ref = 2.302 V and analog to digitlal converter resolution of 24 bits, one ADC count represents 2.302 V/2^24 steps = 137 nV/ADC count.

  • 0 in reply to Jason Work
    TI__Genius 10830 points

    For better performance, Texas Instruments recommends that you limit your input voltage range to 80% of the full-scale range. 

    = 0.8(full-scale range)
    = 0.8*(2*Vsd24ref)
    = 0.8*(2.302 V)
    = 1.84 V

    In this case one ADC count would represent 1.84 V/2^24 steps = 110 nV/ADC count.

  • 0 in reply to Jason Work
    Guru 227245 points

    Jason Work said:
    For better performance, Texas Instruments recommends that you limit your input voltage range to 80% of the full-scale range. = 1.84 V


    I don't think this interpretation is exactly true.

    The absolute input voltage can be from AVss-1V to AVcc on both inputs. However, the differential input voltage (difference between negative and positive input) must not exceed Vref/GAIN (or, for full performance, 0.8Vref/GAIN).

    So (for GAIN=1) if your negative input is GND, the input voltage on the positive input should be between -0.92 and +0.92V, not between 0 and 1.84V.

    If you want to measure voltage between 0V and 1.84V, you must tie the negative input (SDxN) of the SD24 to 0.92V.
    If you tie SDxN to Vref, you'll get full 2.3V input range, but full performance is only guaranteed for the range of 0.23V to 2.09V.

    You can even shift it higher: if AVcc is 3.6V, you can put SDxN to 2.68V and measure the range between 1.76V and 3.6V with maximum performance and full resolution (well, maybe not with maximum performance, as I guess the input differential amplifier will come to its limits then)

  • 0 in reply to Jens-Michael Gross
    TI__Genius 10830 points

    Jens-Michael Gross said:

    For better performance, Texas Instruments recommends that you limit your input voltage range to 80% of the full-scale range. = 1.84 V


    I don't think this interpretation is exactly true.

    [/quote]

    Perhaps I can be more clear.

    Using an input voltage range of 100% of the full-scale range, 1.00*|SDxP0 - SDxN0| <= 1.00*Vsd24ref = 1.151 V
    Using an input voltage range of   80% of the full-scale range, 0.80*|SDxP0 - SDxN0| <= 0.80*Vsd24ref = 0.80*1.151 V = 0.921 V

  • 0 in reply to Jason Work
    Guru 227245 points

    Jason Work said:
    Perhaps I can be more clear.

    You did :)
    (people usually tend to interpret 'full scale range y' as "input voltage from 0 to y", while it really is "from SDxN0-y/2 to SDxN0+y/2". Hence my veto.)
    And thats's basically what the datasheet tells - in less clear words:

    Differential input voltage for specified performance (SD24REFS=1, SD24GAINx=1):   ±920 mV

    So by analyzing the situation from a different angle, we came to the same value as written in the datasheet.

    Which indicates that either both, we and the datasheet, are correct, or that we properly understood how the value in the datasheet was calculated.

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