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TimerA on MSP430F471xx

Salvatore Mazzola
Prodigy 180 points

Considering that setting TACLR resets TAR but also the clock divider and the count direction. Is there a potential conflict if I initialize Timer A in this way ?

    TACTL = TASSEL_1 + MC_0 +ID_3 + TACLR;

Would it be better to do this instead?

   TACTL = | TACLR;

   TACTL = TASSEL_1 + MC_0 +ID_3 ;

Will TACTL be different in the two cases?

  • 0
    Guru 227245 points

    Salvatore Mazzola said:
    Will TACTL be different in the two cases?

    Not TACTL, but possibly TAR, depending on its previous state of TACTL.

    Depending on current configuration, the second way may stop the timer with an unknown count. Imagine an interrup tbetween the two lines in teh second version. The timer was reset but keeps running and counting during ISR execution. Then it is finally stopped by setting it back to MC_0. The first version makes sure that the tiemr is reset and stopped at the same time.

    Also, it is "|=" and not "=|".

    And I recommend using the "|" bit operator and not the arithmetic '+' operator when joining bits or bitfields in an expression.

    "TACLR +TACLR" gives a completely different result than "TACLR | TACLR". And you don't always know (or see at first glance) which bits are already contained in a token. (especially the WDT defines or the LPM defines are prone to cause havoc if you add something to them)

  • 0 in reply to Jens-Michael Gross
    Prodigy 180 points

    OK, but I was also wondering if the first line of code (    TACTL = TASSEL_1 | MC_0  | ID_3 | TACLR;     )  was correct.

    TACLR resets not only TAR but also the clock divider (IDx) 

    Is it OK to set IDx and TACLR at the same time? What happens first?

    Thank you.

  • 0 in reply to Salvatore Mazzola
    Guru 227245 points

    Salvatore Mazzola said:
    TACLR resets not only TAR but also the clock divider (IDx) 

    I'm not really sure about this. I rememebr reading some device errata where it was stated that resetting the timer to 0 (by writing to TAR or setting TACLR) doesn't reset the prescalers and therefore the next count from 0 to 1 may happen at the next clock tick independent of the divider.

    Salvatore Mazzola said:
    Is it OK to set IDx and TACLR at the same time? What happens first?

    Th einternal logic is undisclosed, so I cannot say. It shuld happen mroe or less synchronously.
    However, if the original divider was 0 and you change it to somehting else and the timer clock is asynchronous to MCLK and a timer click hjappens right at the moment you do this operation, it might or might no happen that you get a count, get the prescaler counting, or nothing at all.

  • 0 in reply to Jens-Michael Gross
    Guru 16361 points

    Salvatore Mazzola said:
    TACLR resets not only TAR but also the clock divider (IDx) 

    I think the language used in the user guide is a bit ambiguous here. I read "Setting TACLR also clears the clock divider" to mean that the internal state of the divider circuit is cleared, not the IDx bits. The only reason I settled on that interpretation is that I couldn't come up with a reasonable explanation of why clearing IDx with TACLR would be useful. The IDx bits can simply be cleared directly as required. The divider's internal state, on the other hand, is inaccessible.

  • 0 in reply to Robert Cowsill
    Guru 25210 points

    Robert Cowsill said:
    I think the language used in the user guide is a bit ambiguous here. I read "Setting TACLR also clears the clock divider" to mean that the internal state of the divider circuit is cleared, not the IDx bits. The only reason I settled on that interpretation is that I couldn't come up with a reasonable explanation of why clearing IDx with TACLR would be useful. The IDx bits can simply be cleared directly as required. The divider's internal state, on the other hand, is inaccessible.

    That seems a reasonable interpretation. Usually the reset control bit doesn't reset other accessible register bits, but instead the internal state of the logic that those other bits control.

  • 0 in reply to Robert Cowsill
    Guru 227245 points

    Robert Cowsill said:
    I think the language used in the user guide is a bit ambiguous here. I read "Setting TACLR also clears the clock divider" to mean that the internal state of the divider circuit is cleared, not the IDx bits

    Of course you're right. (and yes, clearing the IDx bits by a bit in the very same register makes no sense. However, the SWRST bit clears the IE bits of the USCI, so these things do happen - for a reason in this case)
    I didn't even think of this interpretation of the bit description.

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