Hello.
Iám trying to write a code for implement a IR 38KHZ receiver using Tsop1138. Te objetive of this project is to control a ceiling lamp which has a fan. That ceiling can be controlled by its remote control but i want to control it with a circuit made by me. At start i used a protoboard with the tsop1138 connect with a 100Ohm resistor and 4,7uf capacitor and the "out" line this tsop connect to P1.2(TimerA input) of MSP430 launch kit with msp430g2553. I use the TimerA in continue mode. The tsop1138 outputs signal at hight and low it when there is a change in signal.
The code doesn´t work correctly becouse it doesn´t detect correctly the 3 signal changes of a bit(low,high and low). It detects low,hight and again "hight" which is wrong.
Bit0:
--------- ------------------------
| | |
| | |
------------ --------------
<--550us-><---1600us---->
Bit1:
--------- --------------
| | |
| | |
--------------------- --------------
<----1600us-----><--550us->
Frame bits:
key 0:
01010101 01010101 00001111
key 1:
01010101 01010101 11110011
key 2:
01010101 01010101 11001111
key 3:
01010101 01010101 00111111
Light on/off key:
01010101 01010101 11000000
speed-up key:
01010101 01010101 11111100
speed-down key:
01010101 01010101 00001100
My code:
#include <msp430.h>
unsigned int tbajada0,tsubida0,tbajada1;
unsigned int tbajo,tciclo,talto;
unsigned int numbitscab,numbitscmd,numflancoscap;
unsigned int iniciosenal,iniciotrama;
unsigned char bitscab,bitscmd;
int main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer
// P1SEL |= BIT0;
P1DIR |= BIT0+BIT6; // P1.0/LED Output
P1OUT &= ~(BIT0+BIT6); // LED off
if (CALBC1_8MHZ==0xFF) // If calibration constant erased
{
while(1); // do not load, trap CPU!!
}
DCOCTL = 0; // Select lowest DCOx and MODx settings
BCSCTL1 = CALBC1_8MHZ; // Set DCO to 8MHz
DCOCTL = CALDCO_8MHZ;
// Configure Port Pins
P1DIR &= ~BIT2; // P1.1/TA0.1 Input Capture
P1SEL |= BIT2; // TA0.1 option select
// Configure the TA0CCR1 to do input capture
TA0CCTL1 = CAP + CM_3 + CCIE + SCS + CCIS_0;
// TA0CCR1 Capture mode; CCI1A; Both
// Rising and Falling Edge; interrupt enable
TA0CTL |= TASSEL_2 +ID_3+ MC_2 + TACLR; // SMCLK, Cont Mode; start timer
// Variable Initialization
numbitscab=0;
numbitscmd=0;
numflancoscap=0;
bitscab=0;
bitscmd=0;
iniciosenal=0;//cambio actual
iniciotrama=1;
tciclo=0;
tbajo=0;
talto=0;
tbajada0=0;
tsubida0=0;
tbajada1=0;
while(1)
{
__bis_SR_register(LPM0_bits + GIE); // Enter LPM0
// __bis_SR_register(GIE);
__no_operation(); // For debugger
// On exiting LPM0
if (TA0CCTL1 & COV){ // Check for Capture Overflow
TA0CCTL1 |=COV; //para salir de overflow
}
//aqui calculamos los tiempos en alto,bajo y del periodo
if(numflancoscap==3){//si capturado un bit
tbajo=tsubida0-tbajada0;
talto=tbajada1-tsubida0;
tciclo=tbajo+talto;
if(tciclo>=17000 && tciclo<=18000){//si duración correcta del bit
if(tbajo>=4400 && tbajo<=4800){
if(talto>=12000 && talto<=14000){
//se trata de un 0
if(numbitscab<16){
bitscab=bitscab<<1;
numbitscab++;
}
else{
bitscmd=bitscmd<<1;
numbitscmd++;
}
}
}
if(tbajo>=12000 && tbajo<=18000){
if(talto>=4000 && talto<=4800){
//se trata de un 1
if(numbitscab<15){
bitscab=bitscab<<1;
bitscab|=0x0001;
numbitscab++;
}
else{
bitscmd=bitscmd<<1;
bitscmd|=0x0001;
numbitscmd++;
}
}
}
}
if(numbitscab==16 && numbitscmd==8){//si trama leida
//P1OUT|=BIT0+BIT6;
iniciosenal=1;
iniciotrama=1;//inicio nueva trama
}
numflancoscap=0;
}
}
}
// TA0_A1 Interrupt vector
#pragma vector = TIMER0_A1_VECTOR
__interrupt void TIMER0_A1_ISR (void)
{
switch(__even_in_range(TA0IV,0x0A))
{
case TA0IV_NONE: break; // Vector 0: No interrupt
case TA0IV_TACCR1: // Vector 2: TACCR1 CCIFG
if (TA0CCTL1 & CCI) // flanco subida
{
P1OUT |=BIT0;
if(iniciosenal){//si puesta a nivel alto de la salida receptor IR.
iniciosenal=0;//desmarcamos el inicio de señal
}
else{//si subida valida capturamos contador
tsubida0=TA0CCR1;
numflancoscap++;
TA0CCR1=0;
}
}
else //flanco bajada
{
P1OUT |=BIT6;
if(iniciotrama){//si primera bajada de la trama capturamos contador
tbajada0=0;
numflancoscap++;
iniciotrama=0;
TA0CCR1=0;
}
else{//bajada intermedia,pertenece al final de un ciclo y al principio del otro
tbajada1=TA0CCR1;
tbajada0=0;
numflancoscap++;
TA0CCR1=0;
}
}
__bic_SR_register_on_exit(LPM0_bits + GIE);
break;
case TA0IV_TACCR2: break; // Vector 4: TACCR2 CCIFG
case TA0IV_6: break; // Vector 6: Reserved CCIFG
case TA0IV_8: break; // Vector 8: Reserved CCIFG
case TA0IV_TAIFG: break; // Vector 10: TAIFG
default: break;
}
}
Please help me if you can.
Thank you.
