47k/2.2nF Reset/SBW

Your understanding is correct. That is what TI recommending.

Actually, neither part is needed for SBW programming. When doing SBW, the RST pin is controlled by the FETs PUSH/PULL output. But any capacitance will affect the SBW signal timing and prevent SBW access if too large.

However, for ensuring proper startup on power-on (without FET attached), a large R/C time constant (Tau) on RST is required. The slower VCC rises, the larger Tau should be, so RST stays below VCC until VCC has settled.

The two uses contradict: 2.2nF is a value that will be sufficient for most cases while not blocking SBW. But in some cases, 2.2nF isn't enough. In this case you may put a series resistor between the R/C and RST while SBW goes directly to RST. This will reduce the influence of C on SBW while still providing a sufficient Tau. 1k should be enough to use 100nF without influencing SBW.