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MSP430F6659: Does the USB module support the external 20MHz XT2 crystal?

Hank Chu
Expert 1340 points
Other Parts Discussed in Thread: MSP430F6659

Nice to meet you!

We are customizing the TI USB BSL for the MSP430F6659 MCU.

The frequency of external XT2 crystal for MSP430F6659 is 20MHz in our H/W design.

1) According to MSP430x5xx and MSP430x6xx Family User's Guide, (Literature Number: SLAU208N), page-1081,

      Table 40-2. Register Settings to Generate 48MHz Using Common Clock Input Frequencies, it said:

>>  CLK_SEL (MHz) : 

>>     ...., 12, 12.8, 14.4, 16, 16.9344, 16.94118, 18, 19.2, 24, 25.6, 26, 32

In the list of CLK_SEL (MHz) supported by MSP430F6659, it does not contain the 20MHz for our H/W design.

Could the USB module of MSP430F6659 support the external XT2 crystal with 20MHz frequency?

Thank you.

 

 

  • 0
    Guru 25210 points

    Hank Chu said:
    Could the USB module of MSP430F6659 support the external XT2 crystal with 20MHz frequency?

    Well, That section of the User's Guide also shows the block diagram and gives you the formula for calculating the output frequency of the PLL based on the input frequency and some prescaler and feedback divider values (See Figure 40-5 and formula 16).

    With that information, and some high-school algebra, it is easy to pop the data into a spreadsheet and calculate all the relevant combinations (all frequency values in MHz):

    Fout 48
    Fin 20
    Fout = Fin * (DIVM/DIVQ)
    Fout/Fin 2.4 =Ratio of DIVM/DIVQ
    DIVQ Required DIVM Floor(DIVM) Ciel(DIVM) Actual Fout (Floor) Actual Fout (Ciel)
    1 2.4 2 3 40 60
    2 4.8 4 5 40 50
    3 7.2 7 8 46.66666667 53.33333333
    4 9.6 9 10 45 50
    6 14.4 14 15 46.66666667 50
    8 19.2 19 20 47.5 50
    13 31.2 31 32 47.69230769 49.23076923
    16 38.4 38 39 47.5 48.75

    As you can see, none of the allowable options get you close enough to 48MHz. Additionally, the DIVQ=16 violates the 1.5MHz min input spec to the PLL.

    Answer: No.

    Hint: Try changing to a 24 MHz XTAL and you will have better luck.

  • 0 in reply to Brian Boorman
    Expert 1340 points

    Thanks for your kind help.

    We got it.

    Please do us a favor to close this case.

  • 0 in reply to Hank Chu
    Guru 25210 points

    Table showing allowable XT2 input frequencies for using the USB PLL for 48MHz output.

    Legend:
    Orange = Violates XT2 Max Input Spec
    Green = OK to use
    Yellow = Cannot be crystal, must use XT2 in Bypass Mode
    Red = Violated USBPLL Min Input Spec

  • 0 in reply to Brian Boorman
    Expert 1340 points

    In the "MSP430x5xx and MSP430x6xx Family, User's Guide" , (Literature Number: SLAU208N), in the Table 40-2,

    it describes a setting as follows:

    >>>> CLK_SEL (Mhz) = 19.2

    >>>> UPQB = 101

    >>>> UPMB = 010011

    But this setting does not exist in the table in the "

    Table showing allowable XT2 input frequencies for using the USB PLL for 48MHz output."

     

    Could you do us a favor to tell us your comment?

    Thank you.

  • 0 in reply to Hank Chu
    Guru 227245 points

    UPQB=101 means /8. (the meaning of UPQB is /1-/2-/3-/4-/6-/8-/13-/16). And UPMB=010011 means *20 (not *19). And the entry is there, on row ‘20’, column ‘8’

     The interesting thing is that UPMB apparently has one bit more than it needs, the MSB always has to be clear as all combination with this bit set lead to invalid conditions..

  • 0 in reply to Jens-Michael Gross
    Expert 1340 points

    Thanks for your information.

    We got it.

    Please do us a favor to close this case.

     

  • 0 in reply to Jens-Michael Gross
    Guru 25210 points

    Jens-Michael Gross said:
     The interesting thing is that UPMB apparently has one bit more than it needs, the MSB always has to be clear as all combination with this bit set lead to invalid conditions..

    The table that I posted was generated in MS Excel by running the formula "backwards" assuming 48MHz output and all combinations of M/Q.

    I also found it interesting that the MSB couldn't be used. Perhaps that is for future compatibility if down the road they design a VCO with lower input frequency specification (or maybe that was the case and the VCO couldn't meet design specs after the part was in initial silicon?).

    Either way, I think that chart would be much better in the User's Guide than the one that they have now.

  • 0 in reply to Brian Boorman
    Guru 227245 points

    Yes, since this chart is a 100% cover, and easily readable, it is definitely better than anything currently found in the users guide.

  • 0 in reply to Jens-Michael Gross
    Expert 1340 points
    Thanks for your kind support.We got it.Please do us a favor to close this case.
  • 0 in reply to Hank Chu
    Guru 25210 points

    Hank Chu said:
    Please do us a favor to close this case.

    FYI - This is a forum, not a support case system. There is no "closing a case" feature, and anyone can continue to add to this topic at any time in the future.

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