We tested msp430f5438a microcontroller in 4 wire SPI in slave mode and found out that any 8 bit code b7 b6 b5 b4 b3 b2 b1 b0
transmitted from MSP430 was received by a host in master mode as b0 b7 b6 b5 b4 b3 b2 b1.
We have 100% confidence in correctness of host software as it was used for other slaves.
Of course we can organize very simple work around by transmission of b6 b5 b4 b3 b2 b1 b0 b7 in order to get b7 b6 b5 b4 b3 b2 b1 b0
but we 'd like to confirm first whether it is hardware problem of this chip and we can rely on this stable repetition.
Could this problem be somehow related to another issue in errata sheet of this microcontroller below even though we don't use always the same code
and use UCB0CTLW0.UCCKPH=0 with the following setup UCB0CTL0 |= UCSYNC+UCCKPL+UCMSB+UCMODE1; ?
Function SPI Slave Transmit with clock phase select = 1
Description In SPI slave mode with clock phase select set to 1 (UCAxCTLW0.UCCKPH=1), after the
first TX byte, all following bytes are shifted by one bit with shift direction dependent on
UCMSB. This is due to the internal shift register getting pre-loaded asynchronously when
writing to the USCIA TXBUF register. TX data in the internal buffer is shifted by one bit
after the RX data is received.
Workaround Reinitialize TXBUF before using SPI and after each transmission.
If transmit data needs to be repeated with the next transmission, then write back
previously read value:
UCAxTXBUF = UCAxTXBUF;
