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What is t sync in ADC12 OF cc430f5137

Waqas Ali Khan
Intellectual 570 points

Other Parts Discussed in Thread: CC430F5137

Hello every one,

I have read the user guide for ADC12 of CC430f5137 in which it is written that for pulse sample mode total sampling time is t_sync + t_sample. I have checked the data sheet and user guide but not found the value for t_sync. As per given diagram in user guide t_sync is equal to the 1 clock cycle.

My question is that its any one know how to calculate this t_sync or just assume it 01 clock cycle in my calculation.

  • 0
    TI__Guru**** 220447 points
    Hello Waqas Ali Khan,

    Tsync is pseudo-defined as 1/2 of a cycle because its value can be one or zero depending on what mode is being used. Tsync occurrs when SHI goes high because SHI could go high asynchronous from the ADC12CLK - so the tsync is just the time between SHI and when the next ADC12CLK pulse is, which is a worst case of one cycle. When you use pulse sample mode with single-channel-repeated or sequence-of-channels-repeated conversions you will encounter the tsync time on your first conversion, but since repeated conversions indicates that you start the next sample and conversion immediately then the ADC12CLk should already be lined up on each successive sample and you wouldn't encounter tsync. So in pulse sample mode you can expect a maximum latency of one clock cycle between SHI going high and the start of sampling.

    Regards.
    Ryan

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