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MSP432 SRAM memory retention in LPM3



Hi

SRAM doesn't seem to keep its state in LPM3. 

Here's my code:

#include "driverlib.h"
#include <stdio.h>
#include <string.h>


uint8_t buffer[20000];


void main(void)
{
    // init code
    [...]

    SYSCTL_SRAM_BANKEN |= SYSCTL_SRAM_BANKEN_BNK7_EN;       // enable ALL the memory banks
    SYSCTL_SRAM_BANKRET |= (SYSCTL_SRAM_BANKRET_BNK1_RET |
                            SYSCTL_SRAM_BANKRET_BNK2_RET | 
                            SYSCTL_SRAM_BANKRET_BNK3_RET |
                            SYSCTL_SRAM_BANKRET_BNK4_RET |
                            SYSCTL_SRAM_BANKRET_BNK5_RET |
                            SYSCTL_SRAM_BANKRET_BNK6_RET |
                            SYSCTL_SRAM_BANKRET_BNK7_RET);    // enable retention for ALL memory banks
    __delay_cycles(1000000);    // wait some time

    memset(buffer, 0x7d, 20000);

    Interrupt_enableMaster();
    SCB_SCR |= SCB_SCR_SLEEPONEXIT;
    // enter LPM4
    SCB_SCR |= (SCB_SCR_SLEEPDEEP);
    __sleep();
    __no_operation();

    // wake-up triggered
    char tmp[32];
    sprintf(tmp, "@0x%x: 0x%x ", (uint32_t)buffer, buffer[0]);
    print_string(tmp);
    sprintf(tmp, "@0x20001fff: 0x%x ", *(uint8_t*)(0x20001fff));
    print_string(tmp);
    sprintf(tmp, "@0x20002000: 0x%x ", *(uint8_t*)(0x20002000));
    print_string(tmp);

    while (1);
}

When I flash the program code and let it run, the output is  0x7d for all 3 memory addresses. However, after resetting the device, the output is different:  I get 'random' values for the last print line, which tells me that bank 1 of SRAM (starts at 0x20002000) does NOT retain its state. 

Regards,

keepcoding

  • Hi keepcoding,

    I do not see where you set the SRAM_RDY bits, writes to the BNKx_RET & BNKx_EN bits are allowed only when the SRAM_RDY bit of the respective register (SYS_SRAM_BANKEN & SYS_SRAM_BANKRET) is set to 1 (per the footnotes in Sections 4.10.6 & 4.10.7 of the User's Guide).

    Regards,
    Ryan

  • Hi Ryan

    Thanks for your reply. However, the SRAM_RDY bit is read only (type 'R') according to the reference manual. So is this wrong then?

    I have tried to set the SRAM_RDY bit before enabling the SRAM banks and retention, but this did not help.

    [edit] I also tried to wait for the SRAM_RDY bit instead of setting it, but then the MCU ends up in an endless loop:

    while (!(SYSCTL_SRAM_BANKEN & SYSCTL_SRAM_BANKEN_SRAM_RDY));    // endless loop

    Regards

  • Hi keepcoding,

    You are correct, I did not interpret the datasheet correctly. The SRAM_RDY bit is read only and cannot be set manually, rather it should be read and checked to indicate whether the SRAM registers are ready for access. Just to confirm, the datasheet is correct.

    What do you define as resetting the device? Is this a power cycle or pressing the reset button on the LaunchPad? Can you provide some screen shots detailing the issue?

    Regards,
    Ryan
  • Hi keepcoding,

    This might be related to one of the SRAM errata we currently have on the experimental silicon. MSP432 Erratasheet: http://www.ti.com/lit/pdf/slaz610

    And I was able to reproduce the same problem:

    keepcoding said:
    When I flash the program code and let it run, the output is  0x7d for all 3 memory addresses. However, after resetting the device, the output is different:  I get 'random' values for the last print line, which tells me that bank 1 of SRAM (starts at 0x20002000) does NOT retain its state

    It seems like after pressing the reset button on the Launchpad the SRAM_RDY bits in both the SYS_SRAM_BANKEN and SYS_SRAM_BANKRET clear to zero, and don't ever return to '1'.  Therefore any attempt to write to SYS_SRAM_BANKRET is ignored.

    Both of the issues are being addressed for the production version of the device. In the meantime please power off/on the board instead of pressing the reset button.

    Hope that helps!

      David

  • Hi David

    Thanks for the clarification. Is there already a release date (or rough time frame) for the MSP432?

    Regards,

    keepcoding

  • Hi keepcoding,

    The best timeframe our marketing department has offered is mid-year 2016: e2e.ti.com/.../1762776

    Regards,
    Ryan

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