here is my code,,,,,,,when i load UCA0TXBUF = 0x01; same time UCA0RXBUF load with "0xff".what is problem with dat..........
is my UCA0BR0 and UCA0BR1 problem .............................
is my clk frequency problem...................i m setting clk frequency 16MHz and baudrate of 9600 so, UCA0BR0 =130 and UCA0BR1 =6.........
here is my code.....and plz tell me cs value should high or low...............................
#include <msp430.h>
#include "math.h"
unsigned int received_ch = 0;
void set_clk();
int SerialPortInit(unsigned long ulBaudRate);
int main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
P5OUT |= BIT0;
P5DIR |= BIT0; // for cs................
P3SEL0 |= BIT0 | BIT1 | BIT2; // Set P3.0,P3.1,P3.2 to non-IO
set_clk(); //.......................................clk set to 16Mhz and 9600 br
// Setup eUSCI_A0
UCA0CTLW0 |= UCSWRST; // **Put state machine in reset**
UCA0CTLW0 |= UCMST | UCSYNC | UCMSB ; // 3-pin, 8-bit SPI master
// Clock polarity high, MSB
UCA0CTLW0 |= UCSSEL_2; // SMCLK
UCA0BRW_L = 130; // /2
UCA0BRW_H = 6; //
UCA0MCTLW = 0; // No modulation
UCA0CTLW0 &= ~UCSWRST; // **Initialize USCI state machine**
UCA0IE = UCRXIE;
//UCCKPH=Clock phase select,UCMSB=MSB first select. Controls the direction of the receive and transmit shift register
//UCMST =Master mode select, 0b = Slave mode,1=Master mode select
//UCSYNC=Synchronous mode enable... 0b = Asynchronous mode...........1b = Synchronous mode
P5OUT &= ~ BIT0; // Select Device
__delay_cycles(1000);
while(!(UCA0IFG & UCTXIFG)); // USCI_A0 TX buffer ready?
//UCTXIFG=Transmit interrupt flag. UCTXIFG is set when UCBxTXBUF empty
UCA0TXBUF = 0x01; // Send 0x01 over SPI to Slave....................................................................................here main prob???? RXBUFF always load with "0xff"
__delay_cycles(10000000);
__bis_SR_register(LPM4_bits + GIE);
}
void set_clk()
{
UCSCTL3 |= SELREF_2; // select .... REFOCLK
UCSCTL4 |= SELA_2; // REFOCLK.....use of Aclk for smclk =SELS_2
__bis_SR_register(SCG0); // Disable the FLL control loop
UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx
UCSCTL1 = DCORSEL_5; // Select DCO range 16MHz operation
UCSCTL2 = FLLD_1 | 487; // Set DCO Multiplier for 8MHz.....making of 16Mhz
// (N + 1) * FLLRef = Fdco
// (243 + 1) * 32768 = 8MHz //(487+ 1) * 32768 = 16MHz
// Set FLL Div = fDCOCLK/2
__bic_SR_register(SCG0); // Enable the FLL control loop
// Worst-case settling time for the DCO when the DCO range bits have been
// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
// UG for optimization.
// 32 x 32 x 8 MHz / 32,768 Hz = 250000 = MCLK cycles for DCO to settle
__delay_cycles(500000);
// __delay_cycles(76563); //for 2.45Mhz
// Loop until XT1, XT2 & DCO fault flag is cleared
do
{
UCSCTL7 &= ~(XT2OFFG | XT1LFOFFG | DCOFFG); //XT2 oscillator fault flag|XT1 oscillator fault flag|DCO fault flag
// Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
} while (SFRIFG1 & OFIFG); // Test oscillator fault flag
}
#pragma vector=USCI_A0_VECTOR
__interrupt void USCI_A0_ISR(void)
{
switch(__even_in_range(UCA0IV,4))
{
case 0:break; // Vector 0 - no interrupt
case 2: // Vector 2 - RXIFG
while (!(UCA0IFG&UCTXIFG)); // USCI_A0 TX buffer ready?
received_ch = UCA0RXBUF;
break;
case 4:break; // Vector 4 - TXIFG
default: break;
}
}
