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The FFT demo run at FR5969

Other Parts Discussed in Thread: MSP430FR5994

This is a FFT demo for FR5969. When the CPU runs at 8MHz, it appears all good. Because of the customer needs faster speed, when I turn the CPU running at 16MHz, there is something wrong with the functions. The code sucked in here.  

/*------------------------------------------------------------------------*/

   /* Zero initialize the output buffer.                                     */

   /*------------------------------------------------------------------------*/

   /*------------------------------------------------------------------------*/

   /* MSP doesn't use memset for code size reasons and the memset won't     */

   /* work for the large code, small data model.                             */

   /*------------------------------------------------------------------------*/

   while(count--) WRITE8_ADV(outbuf, 0);

How can I solve this problem, or do our FFT demo can run at more than 8MHz?

The code I used is here.

#include "msp430.h"

#include <math.h>
#include <stdint.h>
#include <stdbool.h>

#include "DSPLib.h"

/* Global defines */
#define SAMPLES     256
#define FS          4096
#define FREQ1       250
#define FREQ2       1000
#define AMPL1       0.25
#define AMPL2       0.10
#define PHASE1      0.00
#define PHASE2      0.30

/* Input vector A */
DSPLIB_DATA(vectorA,MSP_ALIGN_CMPLX_FFT_Q15(SAMPLES))
_q15 vectorA[SAMPLES*2];

/* Allocate DSPLib parameter structures. */
msp_add_q15_params addParams;
msp_cmplx_fft_q15_params fftParams;

/* Benchmark cycle counts */
volatile uint32_t cycleCount;

void main(void)
{
    float pi;
    float time;
    uint16_t i;
    uint16_t shift;
    msp_status status;
   
    /* Disable WDT. */
    WDTCTL = WDTPW + WDTHOLD;
   
    PJSEL0 |= BIT4 | BIT5;                  // For XT1

    // XT1 Setup
    CSCTL0_H = CSKEY >> 8;                  // Unlock CS registers
    CSCTL1 = DCORSEL|DCOFSEL_4;                     // Set DCO to 16MHz

//    CSCCTL1=DCOFSEL_6;                     // Set DCO to 8MHz
    CSCTL2 = SELA__LFXTCLK | SELS__DCOCLK | SELM__DCOCLK;
    CSCTL3 = DIVA__1 | DIVS__1 | DIVM__1;   // set all dividers
    CSCTL4 &= ~LFXTOFF;

    do
    {
        CSCTL5 &= ~LFXTOFFG;                // Clear XT1 fault flag
        SFRIFG1 &= ~OFIFG;
    }
    while(SFRIFG1 & OFIFG);                 // Test oscillator fault flag
    CSCTL0_H = 0;                           // Lock CS registers

    /* Initialize local variables. */
//    pi = acosf(-1);
    pi = 3.1415926535;
    /*
     * Generate a floating point sine wave and convert to Q15.
     */
    for (i = 0; i < SAMPLES*CMPLX_INCREMENT; i += CMPLX_INCREMENT) {
        time = (float)i/(float)FS;
        CMPLX_REAL(&vectorA[i]) = _Q15(AMPL1*sinf(PHASE1+2*pi*FREQ1*time));
        CMPLX_IMAG(&vectorA[i]) = _Q15(fmod((PHASE1 + FREQ1*time), 1));
        CMPLX_REAL(&vectorA[i]) += _Q15(AMPL2*sinf(PHASE2+2*pi*FREQ2*time));
        CMPLX_IMAG(&vectorA[i]) += _Q15(fmod((PHASE2 + FREQ2*time), 1));
    }
   
    /* Initialize the fft parameter structure. */
    fftParams.length = SAMPLES;
    fftParams.bitReverse = 1;
    fftParams.twiddleTable = msp_cmplx_twiddle_table_256_q15;
   
    /* Call fixed scaling fft function. */
    msp_benchmarkStart(TIMER_A0_BASE, 16);
    status = msp_cmplx_fft_auto_q15(&fftParams, vectorA, &shift);
    cycleCount = msp_benchmarkStop(TIMER_A0_BASE);
   
    /* Check status flag. */
    if (status != MSP_SUCCESS) {
        /* ERROR! */
        while(1);
    }
   
    /* End of program. */
    while (1);
}

 

Thanks!

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