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MSP430G2231: Calibrating and the Errata BCL12 issue

Part Number: MSP430G2231


I'm working on expanding on an idea of Steve Gibson a few years back for filling in the missing 8 MHz calibration value for the G2231 without using a crystal.  Basically, the VLO is used as a standard oscillator.  Of course VLO isn't calibrated, and only its approximate value is known.  But all that matters is that its frequency, whatever it may be, is stable, at least over the short run.  With the clock set at the factory-calibrated 1 MHz settings, you use TimerA to count the number of clocks it takes over, say, 64 ACLK cycles, with ACLK sourced from VLO and divided by 8.  Then you set the clock to your best guess of 8 MHz, change the SMCLK divider for TimerA from 1 to 8, and see if you get the same count for another 64 cycles.  If you don't, you adjust your guess until you do.

This works fine.  The higher calibration values are no better than the accuracy of the 1 MHz value, which I believe is rated at +/- 2%, but that's at a certain temperature and voltage.  But close enough for most government work.  And it turns out  the VLO is indeed pretty stable.  You get essentially the same results when you do this repeatedly on the same chip.

I wanted to expand this to 12 and 16 MHz, and adopt a successive approximation algorithm for arriving at the next guess.  I've got it to the point of performing all three calibrations in less than a second in total, and it seems to work fine on both a G2231 and a G2452.  And on the G2452, the values I get are pretty close the the factory values.

But after reading BCL12 the Errata pdf, I don't think my program should work.  While I do set DCOCTL to zero before stepping RSEL up to 15  (from 14), after that I repeatedly change DCOCTL until I get the best guess, and I don't do any of the other BCL12 "workarounds" for changing DCOCTL.  For the G2452, here's a typical sequence of DCOCTL guesses after the initial zero, with RSEL at 15, all in hex:

20 , 60,  80,  90,  A0,  A8,  AC,  AE,  AF,  B0,  B1   (factory value = AE) 

Since my routine may be used by a number of other people, I want to be sure this doesn't work on my chips just from pure dumb luck, and won't crash large numbers of other chips.  But I've given up on trying to understand the BCL12 writeup, and hope that someone who really understands it can tell me what I need to do, if anything, to make this BCL12-proof.

And from the sequence above, it's clear I need to increase the gain on my difference amplifier.  I think in theory it should be possible to arrive at the answer in four guesses, maybe five.  Successive approximation is pretty neat.

 

  • Hello George,

    To clarify BCL12 errata, if you are increasing RSEL, do this by by one value as you go up in value. This is valid until you want to switch to RESEL value 13. Here you want to follow the note under the table in the errata and switch to RESEL7, then move to RESEL13. From RESEL13 you can move one value up to RESEL14 and form RESEL14 to RESEL15. The table mainly accounts for moving the RESEL value in a downward direction.

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