hello，TI employee
i am using FR2533‘s ADC，and i want to use single sequence of channel modes with Timer B trigger，
but the quesiton is:
1) FR2X/4X series MCU only have one ADC conversion result memory，and DMA do not supported,
this means，in sequence of channel mode ,ADC ISR will be entered each time ADCIFG set when ADC convert complete
2)when using Timer B trigger ADC,according to the UG,ADCENC must be toggled bettween sequence，so when should i toggle the ADCENC.
and my code just the follow:
after the routine executed,the result seems to be wrong that the order of the ADC result in the array is not correct,how should i do ?
/*
@ powered by SS
@Author kissn liu
@date 2017-12-8
@fution:ADC multi channel sample using TA1 trigger;
*/
#include "msp430fr2533.h"
/*
A7-ADC_Result[7]
.
.
.
A0-ADC_Result[0]
*/
unsigned char ADC_Result[8]={0};
void init_ADC_using_TA1_trigger()
{
// Configure ADC A0~7 pins
SYSCFG2 = ADCPCTL0 | ADCPCTL1 | ADCPCTL2 | ADCPCTL3 | ADCPCTL4 | ADCPCTL5 | ADCPCTL6 | ADCPCTL7;
// Configure ADC
//change ADCSHTx bits to change the sample time
ADCCTL0 |= ADCSHT_2 | ADCMSC | ADCON; // 16ADCclks, MSC, ADC ON
ADCCTL1 |= ADCSHS_2 | ADCSHP | ADCCONSEQ_1 | ADCSSEL_0; // ADC clock MODCLK, sampling timer, TA1 trig.,single sequence
ADCCTL2 &= ~ADCRES; // 8-bit conversion results
ADCMCTL0 |= ADCINCH_7 | ADCSREF_0; // A0~7(EoS); Vref=Vcc
ADCIE |= ADCIE0; // Enable ADC conv complete interrupt
ADCCTL0 |= ADCENC; // ADC Enable
TA1CCR0 = 33;
TA1CCR1 = 16;
//TA1CCTL0 = (CCIE);//Enable CCIFG
TA1CCTL1 = OUTMOD_7;//PWM output mode: 7 - reset/set
TA1CTL = (TASSEL__ACLK | MC__UP);
__bis_SR_register(GIE); // Enter LPM3 w/ interrupts
}
void main()
{
WDTCTL = WDTPW | WDTHOLD; // Stop WDT
// Disable the GPIO power-on default high-impedance mode to activate
// previously configured port settings
PM5CTL0 &= ~LOCKLPM5;
init_ADC_using_TA1_trigger();
while(1)
{
}
}
// ADC interrupt service routine
#pragma vector=ADC_VECTOR
__interrupt void ADC_ISR(void)
{
static char i = 7;
switch(__even_in_range(ADCIV,ADCIV_ADCIFG))
{
case ADCIV_NONE:
break;
case ADCIV_ADCOVIFG:
break;
case ADCIV_ADCTOVIFG:
break;
case ADCIV_ADCHIIFG:
break;
case ADCIV_ADCLOIFG:
break;
case ADCIV_ADCINIFG:
break;
case ADCIV_ADCIFG:
/*
When ADCSC triggers a sequence, successive sequences can be triggered by the ADCSC bit.
When any other trigger source is used, ADCENC must be toggled between each sequence.
!!!ADC12ENC must be toggled between sequences
*/
ADCCTL0 &= ~ADCENC;
ADC_Result[i] = ADCMEM0;
if(i == 0)
{
i = 7;
__no_operation();
}
else
{
i--;
}
ADCCTL0 |= ADCENC;
break;
default:
break;
}
}
#pragma vector=TIMER1_A0_VECTOR
__interrupt void TIMER1_A0(void)
{
__no_operation();
}
