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CCS/MSP430F67791A: ADC interrupt timing issue

Shweta Shelar
Prodigy 50 points
Part Number: MSP430F67791A


Tool/software: Code Composer Studio

Dear All,

I had to configure ADC such that i receive ADC Interrupt every 200uSec on completion of A to D Conversion of all  7 Channels.

I have Configured a timer for 200usec wherein

{

SD24BIE |= SD24BIE6 (Enable interrupt on conversion complete of last channel)

}

I have configured my ADC with below settings for 7 Channels available for SD24B in MSP430F67791A .

{

SD24 Clock : SMCLK = 16MHz

OSR : 256

SD24PDIV = 3

SD24DIV = 0

Left Alignment

Group Conversion

SD24BIE = SD24IE6  (In order to receive interrupt on conversion complete of the Last channel)

}

In ADC Interrupt : 

{

Samples are been taken

SD24BIE &=  ~SD24IE6 ;

}

The code works absolutely fine i.e. I receive ADC Interrupt every 200uSec, if I the last channel (Channel 6) reading are not been used.(Interrupt enabled for last channel)

Even if i move the Last channel readings (SD24BMEMH6 & SD24BMEML6) into a temp_Variable , the ADC Interrupt in not obtained every 200uSec (it is almost doubled i.e around 400usec).

It is been observed that for what ever channel SD24BIE |= SD24BIE6 ADC Interrupt is been enabled , this behavior repeats i.e. if interrupt enable been done for 5 th channel  SD24BIE |= SD24BIE5 ,on handling the results of 5th channel (SD24BMEMH5 & SD24BMEML5)  the ADC Interrupt time is altered .

Need your help for solving this issue.

Regards,

Shweta Shelar

  • 0
    Guru 100785 points
    Working backwards: Using (reading) the SD24BMEM register(s) for converter 6 clears IFG6. Conversely, not reading the result register(s) does not clear the IFG -- in this case, the IFG is always pending, so you will always see a "result" (not necessarily a fresh one) every 200usec.

    The remaining mystery is the (2x) longer cycle for getting a true (fresh) sample. My arithmetic, which I suppose matches yours, says that the output rate should be 16MHz/8/1/256=7812.5Hz, or about 128usec/sample. Based on this, there should always be (at least) one output sample over any 200usec period, but that's not what you're seeing, so my guess is that your output rate isn't what you think it is.

    How certain are you that SMCLK is really 16MHz? Are you setting SD24BPRE non-0?
  • 0 in reply to Bruce McKenney
    Intellectual 660 points
    Dear Bruce,

    Thank u for your help.

    I guess the problem is what u have mentioned :
    Working backwards: Using (reading) the SD24BMEM register(s) for converter 6 clears IFG6. Conversely, not reading the result register(s) does not clear the IFG -- in this case, the IFG is always pending, so you will always see a "result" (not necessarily a fresh one) every 200usec.

    The 2x longer cycle is , when u read SD24BMEM register(s) for converter 6 ,when this is set SD24BIE |= SD24BIE6 or
    when u read SD24BMEM register(s) for converter 5,when this is set SD24BIE |= SD24BIE5 and so on.
    For whatever interrupt enable u have set ,If u read SD24BMEM register(s) for that converter, longer cycle is observed.
    If the SD24BMEM Register remains untouched, it give sample properly every 200uSec. (this assures that the sample rate is properly set)

    What can be the work around if I need to read all the SD24BMEM register WITHOUT 2X LONGER CYCLE FOR GETTING A TRUE SAMPLE.

    As I need to read the all the channels for my application.


    Regards,
    Shweta
  • 0 in reply to Prafulla Salunke
    Intellectual 660 points
    Dear Bruce,

    Changing Single conversion to Group Conversion has reduced the delay to 240usec when desired at 200usec

    What can be the probable reason to this issue.
  • 0 in reply to Prafulla Salunke
    Guru 100785 points
    > If the SD24BMEM Register remains untouched, it give sample properly every 200uSec. (this assures that the sample rate is properly set)
    No, it doesn't. Doing this leaves the IFG set all the time, so there's no way to measure the sample (output) rate.

    There are a number of things which can interact to cause a longer output period. Are you setting SD24SNGL? SD24INTDLY? SD24BPRE? How are you triggering?

    If you could post your initialization and ISR code, that would save a lot of guessing.
  • 0 in reply to Bruce McKenney
    Prodigy 50 points
    > If the SD24BMEM Register remains untouched, it give sample properly every 200uSec. (this assures that the sample rate is properly set)
    No, it doesn't. Doing this leaves the IFG set all the time, so there's no way to measure the sample (output) rate.

    Kindly like to highlight that i m reading all channel the SD24BMEM registers except last channel ,then i m getting 200usec.
    If i read the last channel with remaining channels then it show longer time (now with continuous conversion set 240usec)40 usec more


    Adc initialisation settings( mentioned in first mail)

    SD24 Clock : SMCLK = 16MHz

    OSR : 256

    SD24PDIV = 3

    SD24DIV = 0

    Left Alignment

    Continuous Conversion
    Group trigger using SD24BGRP0SC

    SD24BIE = SD24IE6


    Kindly refer the first message for detailed description


    Thanks for ur help
  • 0 in reply to Shweta Shelar
    TI__Guru**** 219477 points
    Hi Praful & Shweta,

    Bruce is requesting your actual code, not just the settings you think that the device is operating at. This way we can remove a lot of the guesswork involved in debugging your issue. Even a simplified example that displays the issue without giving any of your application would be useful in this regard.

    Regards,
    Ryan
  • 0 in reply to Ryan Brown1
    Intellectual 660 points

    Dear Bruce,

    Kindly find the below Archive containing the Code files which i am working on.

    ADC_MSP430F67791A_.zip

    It contains Clock setting , Timer settings, SD24B setting  and their interrupt routines

    In SD24B interrupt routine i have toggled the P1OUT for observing the ADC interrupt time.

    when i comment the below lines i get the ADC interrupt time to be 200usec

    I_Sample[0] = (SD24BMEMH6<<8); // Save CH6 results (clears IFG) 
    I_Sample[0] |= (SD24BMEML6>>8);

    If it remains uncommented it gives interrupt time to be 200usec.

  • 0 in reply to Prafulla Salunke
    Intellectual 660 points
    Sorry, If it remains uncommented it gives interrupt time to be 240usec.
  • 0 in reply to Prafulla Salunke
    TI__Guru**** 219477 points
    Praful,

    Thank you for providing the code. The SD24_B is continuously converting so long as SD24GRP0SC is set, completely independent of an external timer trigger. Bruce's analysis of 128 usec/sample still holds true, but then the group of channels would take 896 usec (7 times as long) to sample. By not reading/storing the SD24BMEMH6 value inside the ISR, the SD24IFG6 remains set but you've manually cleared the SD24IE so the ISR is not re-entered until the Timer A1 interrupt occurs every 200 usec. Regardless of this it is clear that very few of the results will have been sampled and updated properly, my advice is that you revisit sampling frequency requirements and greatly reduce your OSR.

    Regards,
    Ryan
  • 0 in reply to Ryan Brown1
    Intellectual 660 points
    Dear Ryan,

    Thank u for ur reply .I would just try out reducing the OSR and check for the timings..
  • 0 in reply to Prafulla Salunke
    Guru 100785 points
    > SD24BCTL0 = SD24SSEL_1 /* Clock is SMCLK */
    > | SD24PDIV_3 /* Divide by 8 => ADC clock: 2MHz */
    > | SD24DIV0

    SD24DIV0 describes a divisor of 2, not 1. This increases your output period to 256 usec (pretty close to 240 usec measured). Try

    > | (0*SD24DIV0) // SD24DIV_0 -> DIV=1
  • 0 in reply to Bruce McKenney
    Intellectual 660 points
    Hello Bruce,
    Thanks for your help. We are proceeding further with your inputs for further testings. I will get back to you for further assistance.
  • 0 in reply to Prafulla Salunke
    Intellectual 660 points
    Dear Ryan ,

    Tried testing with reduced OSR, getting interrupt every 200usec.

    I had a query regarding the ADC Interrupt interval if put in continuos trigger mode.

    If I have set
    OSR : 128
    CLK : SMCLK : 16MHz
    SD24CLKDIVx : 0
    SD24CLKPDIVx : 3

    what should be the ADC Interval observed.

    According to the calculations
    fM = 16MHz/((SD24CLKDIVx +1)*2^SD24CLKPDIVx ) (as specified in the usermanual)

    fM = 2Mhz

    Sampling rate = fM/OSR = 16384

    Sampling interval : 60usec

    But I am observing 120usec.

    Same is the case when i set OSR as 256

    Expected interval : 120usec but observed is 240usec .

    Am I going wrong with calculations.
  • 0 in reply to Prafulla Salunke
    Guru 100785 points
    > SD24CLKDIVx : 0
    > Same is the case when i set OSR as 256
    >Expected interval : 120usec but observed is 240usec .

    Are you certain that SD24[CLK]DIV=0? This is the measurement you were reporting before with SD24DIV=SD24DIV0 (which is not =0). Your measurement at OSR=128 is also consistent with that setting. Did you make the change I recommended above?
  • 0 in reply to Bruce McKenney
    Intellectual 660 points
    According to datasheet , setting SD24CLKDIVx : 0 corresponds to /1 .

    I had made change as suggested by you but the results are consistent.

    for OSR as 128
    Sampling interval : 60usec

    But I am observing 120usec.

    Same is the case when i set OSR as 256

    Expected interval : 120usec but observed is 240usec .
  • 0 in reply to Prafulla Salunke
    TI__Guru**** 219477 points
    Praful,

    What Bruce is very patiently trying to explain is that SD24DIV0 sets the first bit of the field to a 1, as compared to your expectation of setting all SD24DIVx bits to zero. This is made clear by looking at the MSP430F67791A header file. Therefore SD24DIVx = 0001b which is a divide by 2, resulting in the sampling issue you are observing.

    Regards,
    Ryan

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