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MSP430FR2633: Why I2C SCL pull low?

Poh Kok Keng
Genius 5512 points
Part Number: MSP430FR2633

hi,

I am using register level example code from TI: MSP430FR243x Demo - eUSCI_B0 I2C Master TX bytes to Multiple Slaves.

What i noticed is when it executed to line 250: 1SEL0 |=BIT2 | BIT3, both SCL and SDA did pull high to 3.3V. 

However, once it executed to line 251: P1SEL1 &=~(BIT2 | BIT3), I noticed the SCL line will go low. What is the reason SCL line P1.3 go low after line 251? This is just the initialisation of the i2C GPIO ports. No reason why it should go low. I am expecting both SCL and SDA I2C lines to be high.

Please advice.

Best regards,

KPK

My full test code attached. 

scd30_testing.zip

  • 0
    Guru 26200 points

    Hello Poh,

    <<< However, once it executed to line 251: P1SEL1 &=~(BIT2 | BIT3), I noticed the SCL line will go low. What is the reason SCL line P1.3 go low after line 251? This is just the initialisation of the i2C GPIO ports. No reason why it should go low. I am expecting both SCL and SDA I2C lines to be high.

       P1SEL0 |= BIT2 | BIT3;

       P1SEL1 &= ~(BIT2 | BIT3);

    The above instructions set the primary function (I2C) for P1.2 and P1.3.

    Both the datasheet and user's guide say nothing about setting SCL to low.

    Everything I could find:

    Real issue is how SCL low affects I2C bus during/after power up.
    I would not worry.

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