MSP430F5418A: UART Input Waveform Question

Hi Darren,

Not sure why the device would change the high/low characteristics, unless the other device is doing it.

Do you know what the MSP430 is interfaced to?

To answer your question, here is a link I found very useful and share often.

Hi Dennis,

The SN75C185 has different propagation delays for HIGH/LOW.

When the input signal to the SN75C185 goes from'
1. L->H, the propagation delay for the output to change, is 1.2us typical
2. H->L, the propagation delay for the output to change is 2.5us typical.

When running at 115.2kbits/s baudrate, this is an 8.7us period. Thus, these propagation delays play a part in why the output waveform is not symmetrical.

They have a device connected to the SN75C185, connected to the MSP430. They want to know if the MSP430 UART peripheral will be able to accurately identify each bit (looks like the device samples and takes the majority), when the high time is longer than the low time.

I guess the problem is, if the MSP430 UART peripheral is set to the same baudrate as the data being transferred (115.2kbit/s), then it tries to sample multiple times each bit. But if the HIGH bit is too long, then it might think the LOW bit is actually HIGH, and vice versa.

It is information regarding how the MSP430 samples the bit-stream, when the high/low lengths are different I was hoping for advice on.

The document you provided is good, I am looking through it. But it is based on discrepencies between the baud rates of the two devices. I guess, with the above waveform, as you move closer to the end of the datastream, there is a higher and higher chance these length discrepencies can cause errors in sampled data...but you'd have to do a calculation analysis on the clocks PPM and sampling rate error vs transferred data length to really understand if this is a problem or not, right...?

There are a number of things to consider. First is the bit rate generator.

For best performance you want zero difference in the bit rates of the sender and receiver. Which drives you to a crystal oscillator on both ends.

For best sampling you want to use the x16 mode which means a reference clock of 16 X 115Kbps.

The user guide describes sampling in tiny detail for the low frequency mode but I think it also applies to the x16. Sampling is at N/2 clocks (the middle of the bit time) and 1/2 clock on either side.

Given that you can see what happens. Remember that everything starts with the leading (falling) edge of the start bit. I suspect that so long as the difference in bit clocks is tiny there will be no trouble. If there is a difference then the sampling window will shift over time with respect to the bit edges.