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MSP430FR2155: TimerB generates PWM and an exception occurs

Part Number: MSP430FR2155

Dear team:

One of my customers has the following technical questions, please help to answer:

Timer B generates PWM. When the duty cycle increases, the PWM is normal; however, when the duty cycle decreases, a full cycle high level appears. E.g,
If TB1CCR1 = 100, change to TB1CCR1 = 200, and the duty cycle changes from 25% to 50%, which is normal; but, if TB1CCR1 = 200, change to TB1CCR1 = 100, and the duty cycle first changes from 50% to 100%, then To 25%.

void pwm_init(void)
{
    PM5CTL0 &= ~LOCKLPM5;

    TB1CCR0 = 400-1; // PWM Period
    TB1CCTL1 = OUTMOD_7;// | CCIE; // CCR1 reset/set
    TB1CTL = TBSSEL__SMCLK | MC__UP | TBCLR; // | TBIE; // SMCLK, up mode, clear TBR

    _delay_cycles (200);
    TB3CCR0 = 400-1; // PWM Period
    TB3CCTL5 = OUTMOD_7;// | CCIE; // CCR1 reset/set
    TB3CTL = TBSSEL__SMCLK | MC__UP | TBCLR; // SMCLK, up mode, clear TB

}

Best Regards

  • Updating the duty cycle while the timer is running (which is all the time) is tricky, since depending on the value of TB3R/TB1R it might "miss" and not see the old nor the new CCR1 value. Timer B has the CLLD mechanism to avoid this. [Ref User Guide (SLAU445I) Table 14-8 and Sec 14.2.4.2.1]

    CLLD=1 is usually a good setting. So

        TB3CCTL5 = OUTMOD_7;// | CCIE; // CCR1 reset/set

     becomes

        TB3CCTL5 = CLLD_1 | OUTMOD_7;// | CCIE; // CCR1 reset/set

     

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