How do you DMA from RAM to FLASH on a MSP430?

I think that is a good intuition about the DMA wanting to operate faster than the flash is written. The problem here is there is no flash trigger for the DMA, so if you use the DMAREQ software trigger you have to make sure the timing works out. Using one of the timers is the most common solutions.

I've re-implemented the example using a timer:

#include "msp430xG46x.h"

void main(void)
{
  unsigned short inData[16];
  volatile unsigned int i;
 
  WDTCTL = WDTPW + WDTHOLD;                 // Stop WDT

  FLL_CTL0 |= XCAP14PF;                     // Configure xtal load capacitance

  // LFXT1 startup delay
  do
  {
    IFG1 &= ~OFIFG;                         // Clear OSCFault flag
    for (i = 0x47FF; i > 0; i--);           // Time for flag to set
  }
  while (IFG1 & OFIFG);                     // OSCFault flag still set?
  __disable_interrupt();                    // Disable interrupts
 
  // create some dummy data
  for (i = 0; i < 16; i++)
  {
     inData[i] = i + 1;
  }  

  // Setup Timer_B for DMA to FLASH
  TBCTL = TBSSEL_2;                         // Use SMCLK as Timer_B source
  TBR = 0;
  TBCCR0 = 100;                             // Initialize TBCCR0
  TBCCR1 = 50;                              // Initialize TBCCR0
  TBCCTL1 = OUTMOD_7;                       // Reset OUT1 on EQU1, set on EQU0

  // set up DMA
   __data16_write_addr((unsigned short)&DMA0SA, (unsigned int)inData);
                                            // Start block address
   __data16_write_addr((unsigned short)&DMA0DA, 0x10000ul);
                                            // Destination block address
  DMA0SZ = 0x0010;                          // Block size
  DMA0CTL = DMADT_0 + DMASRCINCR_3 + DMADSTINCR_3 + DMAEN + DMAIE;
                                            // single xfer, inc s & d,
                                            // enable DMA & interrupt
  DMACTL0 = DMA0TSEL_8;                     // TBCCR0 triggers DMA0

  // Setup and erase Flash memory
  // (Rem.: This time is also used to wait for
  //        the voltages getting stabilized)
  FCTL2 = FWKEY + FSSEL1 + FN1;        // SMCLK/3 = ~333kHz
  FCTL3 = FWKEY;                       // Unlock Flash memory for write
 
  FCTL1 = FWKEY + ERASE;
  __data20_write_char(0x10000ul, 0x00); // Dummy write activates segment erase
  
  FCTL1 = FWKEY + WRT;                  // Enable Flash write for copying
  
  TBCTL |= MC0;                           // Start Timer_B in UP mode
                                          // (counts up to TBCL0)

  // Activate LPM during DMA transfer, wake-up when finished
  __bis_SR_register(LPM0_bits + GIE);     // Enable interrupts, enter LPM0
  __disable_interrupt();                  // Disable interrupts

  // Deactivate Flash memory write access
  FCTL1 = FWKEY;                       // Disable Flash write
  FCTL3 = FWKEY + LOCK;                // Lock Flash memory

  TBCTL = 0;                           // Disable Timer_B
}

//------------------------------------------------------------------------------
// DMA interrupt handler
//------------------------------------------------------------------------------
#pragma vector=DMA_VECTOR
__interrupt void DMA_ISR(void)
{
  DMA0CTL &= ~DMAIFG;                       // Clear DMA0 interrupt flag
  __bic_SR_register_on_exit(LPM0_bits);     // Exit LPM0 on reti
}
//------------------------------------------------------------------------------

Note that Timer B is used to produce a square wave with a period of 100 clock cycles (SMCLK = 1.048576 MHz). I tried to reduce this value but the DMA transfer still didn't work even if the period was 80 cycles. This shows how much faster the DMA transfer is compared with the FLASH memory!

Also this version uses the DMA interrupt, which is fired when the transfer is complete, and the ISR to handle it.

Derek