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IRDA Pulse Decoding Hardware on the MSP430F5172

Robert Dickens
Prodigy 50 points
Other Parts Discussed in Thread: MSP430F5172

Hi All,

I'm using the IRDA pulse decoding hardware that forms part of the UART peripheral (USCI A0) on the MSP430F5172. The signal being fed to the decoder originates at the output of a high gain analog op-amp circuit. The output is data sliced by the onboard comparator before ultimately being fed to the UART Rx input. Due to the high-gain of the op-amp circuit there is often some stable, but prominent, ringing associated with pulses that are being amplified by the analog circuitry. When the ringing is conditioned by the comparator, I quite often see the primary signal (with an active high duration of about 8us) being followed by a secondary pulse (with an active high duration of about 5us). There is approximately 7us of time between the two pulses.

For reference, the IRDA decoder is configured to reject pulses shorter than 300ns, and the UART baud rate is currently set to 15kbaud. I'm using SMCLK to drive the peripheral. SMCLK is driven by a 12MHz DCO oscillator that is FLL stabilized against an external 32.768kHz crystal. 

What I would like to know is will there be a problem with the IRDA decoder as it decodes this double pulse signal (where ideally there should only be one narrow pulse being fed through to the decoder)? In other words will the second pulse somehow be decoded as the next bit in the bit train. Remember the double pulse length is only about 20us in duration, in total (8 + 7 + 5), whereas the next bit in the pulse train should only start to be decoded at about 1 / 15000 = 66us. From what I can infer so far, it looks like there is a problem with the second pulse somehow influencing the value of the next bit. I can't confirm this through the debugger though, for reasons that will take too long to explain and I don't think are relevant to the topic. There is no description in the user guide or datasheet relevant to the part, detailing the underlying operation of the IRDA decoding hardware. Thus I am at a bit of a loss as to what is going on, and why multiple pulses within a bit window appear to upset the peripheral. 

Any insight on this problem would be greatly appreciated.

Many thanks,

Robert

  • Guru 58965 points

    To design an IrDA signal conditioning circuit for incoming IR is not a easy task. Aside from the ringing (or double pulse) problem you described, have you tried your circuit under different levels of ambient light? Have you tried it with the transmitter very close by vs far away?

    I strongly suggest that you use (or at least test) a ready made IrDA IR Receiver. It consists of a pin diode, a high-gain bandpass amplifier followed by a discriminator and a pulse shaper specifically designed to mitigate the aforementioned challenges. It is usually packaged together with an IrDA IR Transmitter. This combination is usually called an IrDA Transceiver. Vishay comes to my mind as one of the manufactures of IrDA Transceiver. And there are many others.

  • in reply to old_cow_yellow
    Prodigy 50 points

    Hi old_cow_yellow,

    Thanks for the response. I don't want to stop the question thread with your answer, because it's not quite the information I'm looking for. I take cognisance of all the recommendations you've made, and we have looked at various strategies to mitigate the effects of ringing, and other adverse environmental effects within the circuit. I perhaps should have mentioned it in my original posting, but I'm not actually developing an IrDA remote, nor even using the IrDA protocol in its intended fashion. Suffice to say the IrDA encoder/decoder hardware on the MSP430F5172 happens to give me the shaped signal train that I need, in more or less the fashion I need it.

    I return to my original question, does anybody know the internal workings of the hardware block of the IrDA decoder? I'd like to know if the double pulse that occurs well within the first half of a bit period (as per my original posting) is going to affect the signal construction of the UART packet that is routed to the UART peripheral. My findings thus far seem to indicate yes, but it would be ideal if I could confirm that this is actually the case, and why it is the case if so. ie. How does the hardware block work?

    Regards,

    Robert

  • in reply to Robert Dickens
    Guru 58965 points

    Robert,

    I do not know how the IrDA decoder in MSP430 is implemented and cannot answer your question. But I do know how it should be implemented.

    Yes, you are correct in saying that the double pulse you have should not be a problem for the decoder. A properly implemented IrDA decoder should behave like an edge triggered one-shot of precisely one bit time. It should not re-trigger during the first half of that one-bit time, but it should re-trigger during the second half of that one-bit time if another pulse comes in. From your experienced problem, it sounds like that decoder is not properly implemented. I suspect that you will find other problems with it.

    If you slow down the clock of the UART and use a Timer with much faster clock to generate fake input for the IrDA decoder, you may be able to study how that decoder behave.

    --OCY

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