MSP430 Internal Flash memory...General questions

Thnx for your replies.

Just to make sure that I got everything right.

The minium number of erase cycles for '0-bit' segments is 10K (the worst case).  This number can be improved by having 1-bit cells (which is typical in real life).

Feel free to correct me if I am wrong.

Yad Tahir said:

This number can be improved by having 1-bit cells (which is typical in real life).

This is wrong to assume that msp430 flash cells are multilevel just because they have comparably low 10k cycle endurance. You can't directly compare flash memory chips and their specs to flash microcontrollers.

Ilmars said:

This is wrong to assume that msp430 flash cells are multilevel just because they have comparably low 10k cycle endurance. You can't directly compare flash memory chips and their specs to flash microcontrollers.

Indeed, multi-level cells have a lower endurance because the wear-out that causes the limited endurance affects the internal signal levels. And if you have multiple leves per cell, the safety margien is obviously smaller.
However, on flash storage, you usually have a controller with wear leveling. that means the controller will rearrange the flash segments to evenly distribute the number of erase cycles. Which of course will only work if there is some spare area, so if a segment is overwritten, a different unused segment with less write cycles is remapped instead and the one that was previously used goes back to the pool. That's why an USB stick with 8GiB capacity offers only 7.5GiB of storage.

On a microcontroller, the flash is fixed to the address space. And some segments are more often rewritten than others, like the one with the interrupt vector table.

Well, of all flash devices I used so far, I've either seen a fault right after using it the first few times (usually USB sticks, including a rather expensive TDK stick) or never.
Not even for the device that writes data to its own flash every few seconds. Well, it's only a few segments per hour, so I'm probably still below the 10k cycles.

Jens-Michael Gross said:

Indeed, multi-level cells have a lower endurance because the wear-out that causes the limited endurance affects the internal signal levels. And if you have multiple leves per cell, the safety margien is obviously smaller.

So you say that msp430 uses Multi Level Cell flash?

Ilmars said:

So you say that msp430 uses Multi Level Cell flash?

If you discover that MSP cycle endurance is less than that of devices with single-level tecnology (and same production technology), then this might be an indicator for the use of multi-levle cells. But no proof for one or the other case.

However, there possibly is a simple check:
Write 0x02, 0x01 to one byte and 0x01, 0x02 to another (without an erase in-between) and check the outcome. For single-level technology, in both cases after the second write the cells will return 0x00. In multi-level technology, they probably won't. At least if two adjacent bits are stored in the same cell (you cyn extend the pattern to cover all possible bit combinations). So if you don't get 0x00 on both bytes after the second write, you will definitely have a multi-level cell structure.

Some 25 years ago, I offered a DMA ram extension. (boosting the capacity of a 256k or 512k DMA module for the C64 to up to 2MB). I wrote a ram test program that did some similar test and discovered shortcuts between different ram banks or bits or addresses due to improper soldering of the extension pack. After 5 minutes of testing, I was able to blindly point at the error location just by looking at the test results.
Years later, this program even discovered a bug in the simulated ram extension module of a C64 emulator on PC. :)
Proper testing patterns tell a lot about the internal structure.

Folks,

I am not aware of the MSP430 being architected with MLC Flash technology.  The E/W Endurance specification is more a result of process technology and overall device reliability, not an assumption that is strictly MLC Flash based.

Also, these days, MLC is more widely designed into NAND-type Flash memory, not NOR-type found in most Flash-based microcontrollers.  Of course, with FRAM technology gaining traction in TI's MCU lineup, the endurance spec is practically a moot point.

Here is a decent Flash memory explanation, for reference:

http://en.wikipedia.org/wiki/Flash_memory

Regards,

Chris

Chris Yorkey said:

I am not aware of the MSP430 being architected with MLC Flash technology. 

My MP3 player had the first (audible!) bit failures in stored MP3 files less than one year after putting the files on it. I encontered similar problems on several USB flash drives with large capacities (where MLC technology is to beexpected). Older (small capacity) SLC devices still have their data intact. MLC is cheaper and smaller, but for backup, I'd chose SLC devices.
Also, AFAIK SLC is used for fast solid state disks, as it is (again otherwise same circumstances) significantly faster than MLC. For a price.