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MSP430F6438 Interrupt Latency?

Other Parts Discussed in Thread: MSP430F6438

Some background:  We have an application that needs to get in & out of interrupts very quickly.  In some initial tests, we saw that it was taking far too long to do this.  We're running a MSP430F6438 at 20 MHz, and it takes pretty much exactly one microsecond to get from an infinite loop into the ISR and toggle an I/O line.  Looking at the assembly, it's 6 instructions (entry to ISR), 4 instructions to flip the I/O pin.  That should take half a microsecond with a 20 MHz clock.  We're seeing it take a full microsecond. Trying to figure out what I have configured incorrectly.  Any thoughts would be greatly appreciated.

Below is the code that I used to test this and the trace from the oscilloscope that was hooked up.  Yellow trace is a 1 KHz square wave, pink trace is the MSP430F6438 output line.

#include <msp430.h> 
/*
* main.c
*/
int main(void) {
WDTCTL = WDTPW | WDTHOLD; // Stop watchdog timer
//Enable 20 MHz oscillator on XT2
int timeout = 5000;
//Enable 20 MHZ oscillator.
P7SEL |= BIT2 | BIT3;
//Enable XT2 Clock
UCSCTL6 &= ~XT2OFF;
//Configure FLL to be 1:1 with XT2, sourced by XT2
UCSCTL3 = SELREF_5;
//Wait for XT2 fault to clear.
do
{
UCSCTL7 &= ~(XT2OFFG | XT1LFOFFG | XT1HFOFFG | DCOFFG);
SFRIFG1 &= ~OFIFG;
timeout--;
}
while ((SFRIFG1 & OFIFG) && timeout);
//Source SMCLK, MCLK, ACLK from XT2
UCSCTL4 = SELM_5 | SELS_5 | SELA_5;

//Wire P4.0 into CCR
P4SEL |= BIT0;
P4DIR &= ~BIT0;
TB0CCTL0 = CM_3 | CCIS_0 | CAP | SCS | CCIE;
TB0CTL = TBCLGRP_0 | CNTL_0 | TBSSEL_2 | ID_0 | MC_2 | TBCLR;
//Wire P1.1 to be output
P1DIR |= BIT1;
P1SEL &= ~BIT1;
P1OUT &= ~BIT1;
_enable_interrupts();
for(;;)
{
_nop();
}
}

#pragma vector = TIMER0_B0_VECTOR
__interrupt void Interrupt_Timinig()
{
P1OUT = (P4IN & BIT0) << 1;
}


 
  • I think you make a few bad assumptions...

    1. You assume that it takes 0 time from the change in input on P4 until the ISR is triggered. This is not what happens. The signal must be clock synchronized and compared, then the logic has to generate the interrupt event to the CPU (at least another clock cycle, probably more). For instance, in the 5xx series, it takes 6 clock cycles for interrupt request (cycles needed before first instruction)

    2. You assume (based on your statement above) that each instruction is only 1 clock cycle. This is also not true. Take a look at the section titled "MSP430 Instruction Execution" in your user's guide.

    1 microsecond is 20 clock cycles at 20 MHz. I can see this being reasonable response time of the MSP430.

    Now, whether this is fast enough for your application is a different story. That's for you to work out.

  • Good response.

    Not sure where I got the idea in my head that ALL instructions take 1 cycle (read through the CPUX instruction portion in my MSP430 datasheet).  Based on what I now know, yeah, that's pretty much the absolute fastest we're going to be able to respond to an interrupt.  That might work for my application.

    Thanks for the help!

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