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MSP430F4152 setting baud rate

Other Parts Discussed in Thread: MSP430F4152

I am confused by what I am seeing going on with my project and I am hoping someone can clue me in.

I have an MSP430F4152 with the SMCLK set to 4 MHz (128 X ACLK[32768]) and want to drive the UART at 115200.  Reading the manual indicates that I need to set the prescalar, UCA0BR0 = 36, and the fractional portion, UCBRS = 3.  However, I can't get any of my devices to run at this setting, which, on its own, is not a big deal.  But, I am finding that I have to "tune" UCA0BR0 for each and every device!  Once I find a setting that doesn't spit out garbage, I can find a narrow range, say UCA0BR0 = 25 - 28, that works while being relatively insensitive to UCBRS for a single device!  I load another device and I find that it wants UCA0BR0 to be within 31 to 34.  This seems crazy to me.  The 32768 crystals (Citizen CM315) that I have on the boards are rock solid.  I've tried using the oversampling mode to set the baud rate, but I can't find any setup that works (following the directions in the UM produces garbage).

Here is the initialization routine (well...at least for one of the deivces) for the UART:

void uart_init(void)
{
UCA0CTL1 = UCSWRST; // put into reset
UCA0CTL0 = 0x00; // 8N1
UCA0CTL1 |= UCSSEL_2; // Use SMCLK
UCA0BR0 = 29; // 4MHz 115200
UCA0BR1 = 0; // 4MHz 115200
UCA0MCTL = UCBRS_4; // Modulation
P6SEL |= BIT5+BIT6; // P6.5,6 = USCI_A0 RXD/TXD
UCA0CTL1 &= ~UCSWRST; // take out of reset
//IE2 |= UCA0RXIE; // Enable USCI_A0 RX interrupt
}

I am sure it is something that I am doing or not doing.  Any help is greatly appreciated.

Thanks in advance.

  • Hi Fran, 

    with this much BR0 variance, I would look at the clock sourcing the peripheral first.  Presuming that the dco is sourcing mclk, take aclk and mclk out to their IO pins (pin tables begin on page 8 Of the DS) to be scoped.   Do this for multiple devices and after the dco has been configured for the 4mhz output.

    let us know what you find.

  • OK, it will take me a day or two to get there.  It's all asses and alligators here at the moment.

    I'll post what I find.

  • In addition to what Michael suggested, it would be helpful to see the code you are using for configuring the UCS clock module. You may not be setting the DCO/FLL registers properly.

  • Here's all I'm doing to init the clock.

    int __low_level_init(void)
    {
      volatile unsigned int i;                  // Use volatile to prevent removal by compiler optimization

      WDTCTL = WDTPW + WDTHOLD; // disable the watchdog
      // Setup the Clocks and Xtal
      FLL_CTL0 |= XCAP11PF;                     // Configure xtal load caps
      for (i = 0; i < 10000; i++);              // Delay for 32 kHz crystal to stabilize
     
      // Loop until Xtal fault is clear
      do
      {
        IFG1 &= ~OFIFG;                         // Clear osc fault flag
        for (i = 0; i < 1000; i++);             // Delay for osc to stabilize
      } while(IFG1 & OFIFG);                    // Check to see if osc flag is set
      

      SCFQCTL = SCFQ_4M;                        // DCO 4.183MHz
     
      
      return (1);                       // Initialize RAM locations.
    }

    It wasn't clear to me from the UM as to what else to do to the FLL registers, but that's probably my deficiency.

    Also, I've made some quick measurements on ONE board.  ACLK is pretty good at 32771, but SMCLK is running at a stable 3.029 MHz, when set up for 4 MHz.  When I change it to SCFQ_2M, it's at 2.04 MHz.

    Not sure what any of that means at the moment, just regurgitating what I see.

  • Fran,

    Try adding 

    SCFI0 |= FN_2;

    to your 4MHz initialization and re-check 

  • Wow!  What a difference.  I now have a solid 4.194 MHz.  I guess the default DCO range specification of 0.65 to 6.1 MHz was not good enough.

    Hopefully, when I move this over to the other devices, my BR0 wobble disappears.

    Thanks for the help!

  • Well, that looks like it's it.  I'm 3 for 3 in setting up the UART with the same parameters on 3 devices.

    Thanks, again, for the help.

    Fran

  • I guess the default DCO range specification of 0.65 to 6.1 MHz was not good enough. If you look at the datasheet, you’ll see that 0.65 to 6.1MHz is a typical value. However, best case it may go from 0.3 to 11.3MHz (if this can be called “best case“, as it means the individual frequencies are far apart) and worst case, It only spans 1.25 to 2.7MHz

    Setting FN_2, the worst case (narrowest) range is from 2.5 to 6.5MHz.

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