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Help with MSPFR5969 ADC Conversion Results

Other Parts Discussed in Thread: MSP-EXP430FR5969

Hi there,

I am very new to the MSP430 and I am a bit confused by how the 12-bit ADC works. I have an MPC9700 thermistor hooked up to my MSP-EXP430FR5969 Launchpad and I am using the following code example to test it:

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//******************************************************************************
//  MSP430FR59xx Demo - ADC12, Sample A1, 1.2V Shared Ref, Set P1.0 if A1 > 0.5V
//
//  Description: A single sample is made on A1 with reference to internal
//  1.2V Vref. Software sets ADC12SC to start sample and conversion - ADC10SC
//  automatically cleared at EOC. ADC12 internal oscillator times sample (16x)
//  and conversion. In Mainloop MSP430 waits in LPM0 to save power until ADC12
//  conversion complete, ADC12_ISR will force exit from LPM0 in Mainloop on
//  reti. If A1 > 0.5V, P1.0 set, else reset.
//
//                MSP430FR5969
//             -----------------
//         /|\|              XIN|-
//          | |                 |
//          --|RST          XOUT|-
//            |                 |
//        >---|P1.3/A1      P1.0|-->LED
//
//   William Goh
//   Texas Instruments Inc.
//   February 2014
//   Built with IAR Embedded Workbench V5.60 & Code Composer Studio V5.5
//******************************************************************************
#include <msp430.h>

int main(void)
{
  WDTCTL = WDTPW | WDTHOLD;                 // Stop WDT

  // GPIO Setup
  P1OUT &= ~BIT0;                           // Clear LED to start
  P1DIR |= BIT0;                            // P1.0 output
  P1SEL1 |= BIT3;                           // Configure P1.3 for ADC
  P1SEL0 |= BIT3;

  // Disable the GPIO power-on default high-impedance mode to activate
  // previously configured port settings
  PM5CTL0 &= ~LOCKLPM5;

  // By default, REFMSTR=1 => REFCTL is used to configure the internal reference
  while(REFCTL0 & REFGENBUSY);              // If ref generator busy, WAIT
  REFCTL0 |= REFVSEL_0 | REFON;             // Select internal ref = 1.2V
                                            // Internal Reference ON

  // Configure ADC12
  ADC12CTL0 = ADC12SHT0_2 | ADC12ON;
  ADC12CTL1 = ADC12SHP;                     // ADCCLK = MODOSC; sampling timer
  ADC12CTL2 |= ADC12RES_2;                  // 12-bit conversion results
  ADC12IER0 |= ADC12IE0;                    // Enable ADC conv complete interrupt
  ADC12MCTL0 |= ADC12INCH_3 | ADC12VRSEL_3; // A1 ADC input select; Vref=1.2V

  while(!(REFCTL0 & REFGENRDY));            // Wait for reference generator
                                            // to settle

  while(1)
  {
    __delay_cycles(5000);                    // Delay between conversions
    ADC12CTL0 |= ADC12ENC | ADC12SC;         // Sampling and conversion start
    __bis_SR_register(LPM0_bits + GIE);      // LPM0, ADC10_ISR will force exit
    __no_operation();                        // For debug only
  }
}

#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector = ADC12_VECTOR
__interrupt void ADC12_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(ADC12_VECTOR))) ADC12_ISR (void)
#else
#error Compiler not supported!
#endif
{
  switch (__even_in_range(ADC12IV, ADC12IV_ADC12RDYIFG))
  {
    case ADC12IV_NONE:        break;        // Vector  0:  No interrupt
    case ADC12IV_ADC12OVIFG:  break;        // Vector  2:  ADC12MEMx Overflow
    case ADC12IV_ADC12TOVIFG: break;        // Vector  4:  Conversion time overflow
    case ADC12IV_ADC12HIIFG:  break;        // Vector  6:  ADC12BHI
    case ADC12IV_ADC12LOIFG:  break;        // Vector  8:  ADC12BLO
    case ADC12IV_ADC12INIFG:  break;        // Vector 10:  ADC12BIN
    case ADC12IV_ADC12IFG0:                 // Vector 12:  ADC12MEM0 Interrupt
      if (ADC12MEM0 >= 0x6B4)               // ADC12MEM = A1 > 0.5V?
        P1OUT |= BIT0;                    // P1.0 = 1
      else
        P1OUT &= ~BIT0;                     // P1.0 = 0
      __bic_SR_register_on_exit(LPM0_bits); // Exit active CPU
      break;                                // Clear CPUOFF bit from 0(SR)

    case ADC12IV_ADC12IFG1:   break;        // Vector 14:  ADC12MEM1
    case ADC12IV_ADC12IFG2:   break;        // Vector 16:  ADC12MEM2
    case ADC12IV_ADC12IFG3:   break;        // Vector 18:  ADC12MEM3
    case ADC12IV_ADC12IFG4:   break;        // Vector 20:  ADC12MEM4
    case ADC12IV_ADC12IFG5:   break;        // Vector 22:  ADC12MEM5
    case ADC12IV_ADC12IFG6:   break;        // Vector 24:  ADC12MEM6
    case ADC12IV_ADC12IFG7:   break;        // Vector 26:  ADC12MEM7
    case ADC12IV_ADC12IFG8:   break;        // Vector 28:  ADC12MEM8
    case ADC12IV_ADC12IFG9:   break;        // Vector 30:  ADC12MEM9
    case ADC12IV_ADC12IFG10:  break;        // Vector 32:  ADC12MEM10
    case ADC12IV_ADC12IFG11:  break;        // Vector 34:  ADC12MEM11
    case ADC12IV_ADC12IFG12:  break;        // Vector 36:  ADC12MEM12
    case ADC12IV_ADC12IFG13:  break;        // Vector 38:  ADC12MEM13
    case ADC12IV_ADC12IFG14:  break;        // Vector 40:  ADC12MEM14
    case ADC12IV_ADC12IFG15:  break;        // Vector 42:  ADC12MEM15
    case ADC12IV_ADC12IFG16:  break;        // Vector 44:  ADC12MEM16
    case ADC12IV_ADC12IFG17:  break;        // Vector 46:  ADC12MEM17
    case ADC12IV_ADC12IFG18:  break;        // Vector 48:  ADC12MEM18
    case ADC12IV_ADC12IFG19:  break;        // Vector 50:  ADC12MEM19
    case ADC12IV_ADC12IFG20:  break;        // Vector 52:  ADC12MEM20
    case ADC12IV_ADC12IFG21:  break;        // Vector 54:  ADC12MEM21
    case ADC12IV_ADC12IFG22:  break;        // Vector 56:  ADC12MEM22
    case ADC12IV_ADC12IFG23:  break;        // Vector 58:  ADC12MEM23
    case ADC12IV_ADC12IFG24:  break;        // Vector 60:  ADC12MEM24
    case ADC12IV_ADC12IFG25:  break;        // Vector 62:  ADC12MEM25
    case ADC12IV_ADC12IFG26:  break;        // Vector 64:  ADC12MEM26
    case ADC12IV_ADC12IFG27:  break;        // Vector 66:  ADC12MEM27
    case ADC12IV_ADC12IFG28:  break;        // Vector 68:  ADC12MEM28
    case ADC12IV_ADC12IFG29:  break;        // Vector 70:  ADC12MEM29
    case ADC12IV_ADC12IFG30:  break;        // Vector 72:  ADC12MEM30
    case ADC12IV_ADC12IFG31:  break;        // Vector 74:  ADC12MEM31
    case ADC12IV_ADC12RDYIFG: break;        // Vector 76:  ADC12RDY
    default: break;
  }
}

I am receiving values in the range of ~1900-2048ish in the ADC Memory register (or, 0x76C - ~0x800). According to my thermistor datasheet, I should be expecting 500mV + 10mV per degree Celcius. I am operating this device at room temperature and I should be expecting to see results in the range of 700-750mV as a result.

Would someone be able to help me understand how the ADC is performing these conversions and arriving at these values?

Thank you in advance,

Mike

  • I'm wondering a little bit about your configuration and the comments you wrote beside your code:

    ADC12MCTL0 |= ADC12INCH_3 | ADC12VRSEL_3; // A1 ADC input select; Vref=1.2V

    Your comments say A1 with 1.2V internal reference. But your code says VeREF+/AVss and A3.

    This would be the correct configuration:

    ADC12MCTL0 |= ADC12INCH_1 | ADC12VRSEL_1; // A1 ADC input select; Vref=1.2V

    Dennis

  • Hi Dennis,

    Thank you for your response. I am working with some example ADC code I found for the MSP430FR59XX series and I appear to have forgotten to adjust the comments. That doesn't mean what I changed was correct though!

    According to the User's Guide for my Launchpad, analog channel A3 is located on P1.3, which is the pin that I am using for my thermistor. The original example code (shown by the comments) was using channel A1 and 1.2V Vref.  So if I wanted channel A3 and 1.2Vref would this be correct?:

    ADC12MCTL0 |= ADC12INCH_3 | ADC12VRSEL_1; // A1 ADC input select; Vref=1.2V

    However, running this code yields values in the 2400's now.

  • Do you have a schematic of that?

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