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SPI timing tCHSL

Hithesh
Genius 3290 points

I was looking up datasheet of SPI Flash. The timing diagram has tCHSL : S# not active hold time (relative to C)

What exactly is this. According to the timing diagram, this is measured between rising edge of clock and S# going high to low.

But this never happens. Clock is 'off' when S# is High.

Figure 3 in "AC Characteristics" in link below - 

www.micron.com/.../{0F7AD04B-73A4-45FA-A2A0-B19F77B3A42B}

  • 0
    TI__Guru 56685 points
    Hello Hithesh,

    Please be aware that this forum is for Texas Instrument's MSP microcontroller products. The SPI Flash you linked to and are asking about is not manufactured by TI. As such, you may not receive proper responses to your inquiry. It is recommended that you go through the SPI Flash's manufacturer's appropriate channels to find a solution to your issue.

    Regards,
    JH
  • 0
    Prodigy 10 points

    Hithesh said:

    But this never happens. Clock is 'off' when S# is High.

    C (clock) is NOT necessarily 'off' when S# is high. Remember SPI supports multiple slaves, where each one might use a different clock and phase configuration, which means Micron has to specify timings for all possible cases that may affect the operation of its chip.

    They are using tha same chart for both mode 0 and mode 3. That's why they show two S# asserting and two S# deasserting edges.

    tCHSL applies only to the serial clock mode in which the clock is normally high when idle, meaning the clock is high before asserting (lowering) S#.

    In this mode, it refers to how much time you have to wait from taking the clock high to its idle state (SCLK initialization,multiple salves, or after the last command) before you can take S# low. It is not a clock cycle per se and in fact tCHSL ensures that it doesn't get erroneously recognized as the first clock rising edge.

  • 0 in reply to TinTronic
    Genius 3290 points

    After taking a closer look at the waveform, it does look like they squeezed Mode 0 and Mode 3 timing into one. I took a look at Atmel flash datasheet, they separate out the 2 modes. No tCHSL or tSHSL (set up time). 

    Thanks for the answer.

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