MSP430G2231 ADC10 ADC10CLK Output Drive Specs

Dan K said:

Does anyone know what/where the specs are for the ADC10's ADC10CLK output signal

One question: what are you talkign about? The ADC10CLK is an internal signal and you cnanot measure it anywhere. I just looked at the schematics once more, but there is nothing that will output the ADC10CLK signal.

I just checked the P1.4 wiring, and indeed there's something written as ADC10CLK, but then, a closer look at the function table below the schematic reveals that it should read ACLK instead (P1SEL.3 = 1, P1DIR.3=1), at least if the name tags on the schematics are correct.

There is definitely a bug in the datasheet. You should report it :)

The AD10 schematic in the users guide does not show any output of the ADC10CLK signal and the registers description does not show any way to output it.

What I can guess (and it's really a guess this time, not even an educated one) is that what you're seeing is the ACLK signal with additional divider. And while the ADC was clocked by SMCLK, ACLK wasn't used by anyone and therefore shut off.
It does not, however, explain the strange duty cycle you observed.

However, the examples are for 20x2 and you're using a 2231, so chances are (as with most TI examples) that the sample code will do comething completely unexpected if not executed on exactly the device it was written for and without any change. The 2231 may have completely different pin assignments and signal routings, even if the internal modules are identical.
And indeed, the 20x2 P1.4 pin schematics shows that there not ACLK is routed to the pin, but ADC10CLK. Bu tonly on the 20x2 processors and neither on th e 20x1 nor 20x3 nor the 22xx types.

 

Jens-Michael Gross said:

  One question: what are you talkign about? The ADC10CLK is an internal signal and you cnanot measure it anywhere. I just looked at the schematics once more, but there is nothing that will output the ADC10CLK signal.

If you look at Table 2, Terminal Functions in the MSP430G2x31/MSP430G2x21 datasheet (SLAS694C), the ADC10CLK signal is described as the conversion clock output on P1.3. Also, in Table 19, Port P1 (P1.3) Pin Functions -- MSP430G2x31, is described how to configure the P1DIR.x, P1SEL.x, and ADC10AE.x signals to output ADC10CLK (CAPD.y does not apply for the MSP430G2x31 - I filed a bug report on that). I have coded my test programs to account for the device I'm using (MSP430G2231). Indeed, as stated previously, I can measure/see ADC10CLK when using ACLK (with 32Khz or VLOCLK) as the ADC10 clock source, but not with MCLK or SMCLK as the ADC10 clock source.

Although the ADC10 block diagram (Figure 20-1) in the the MSP430x2xx Family User's Guide does not show the ADC10CLK actually going to an output pin, generally, my observation is that these block diagrams do not show the signals connections to the device pins (the USI block diagrams are an exception to this, except for their I2C SCLK connection to the P1.5 pin).

As for the strange duty cycle observed on the ADC10CLK output signal with a non-divide-by-1 setting, I have no issue with that except that it does not appear to be documented anywhere. Since the ADC10DIV divider is not a binary divider (1/2/4/8...), a 50% duty cycle is much more difficult to achieve (and likely not necessary).

Again, my issues are with the non-documented ADC10CLK output slow slew rate, drive specifications, and signal timing and how I can get documentation for it.

 

Dan K said:

If you look at Table 2, Terminal Functions in the MSP430G2x31/MSP430G2x21 datasheet (SLAS694C), the ADC10CLK signal is described as the conversion clock output on P1.3.

Yes. And that's why I wrote that there is a bug in the datasheet.

If you look at the DIAGRAM, you'll see that there is not ADC10CLK signal routed anywhere. The signal that comes in if P1SEL.3 is set, is ACLK. And this is compliant to your observations: as soon as you assign ACLK to a module (any module, that is), ALCK is activated and output to the port pin. It is unimportant that you used ACLK as input for the ADC10, you could select it as input for the WDT or a timer as well and you would see it on this pin, even if ADC10CLK is from somewhere else.

I guess the tables were a copy&paste error from other datasheets of the same family, while the diagram has been created explicitely for this particular MSP and is therefore more correct. And it fits your observation of a signal coming only if ACLK is active.

The diagrma, however, might as well be wrong and copied from P1.0 (which has ACLK as signal) with a copy&paste error here (not changing the ACLK input signal to ADC10CLK. Only the TI engineers may know.

Dan K said:

As for the strange duty cycle

This one indeed seems to indicate that you're seeing the ADC10CLK. And indeed, the clock (as it is an internal signal) does not need a duty cycle of 50%. It only needs to trigger the conversion steps. It will, however, not explain why you're not seeing the ADC10CLK if ACLK is inactive. Since ADC10CLK is selected BEFORE the clock is divided. So either you see ADC10CLK, then no matter whether you select ACLK, SMCLK or ADC10OSC, or you're not seeing ADC10CLK, but then where comes the divided signal from.

There's only one explanation that makes some sense (as both observations virtually exlude each other): there is a bug in the silicon that intermixes the ADC10CLK output with the existence of ACLK, maybe as a remainder of other MSPs, where ADC10CLK is usually not availbale externally.
It's worth a call to the TI engineers.

Anyway, since the P1SEL.3 selects a signnal which is routed through the normal digital output, it shouldn't come with a slowly raising edge. The edges should be as steep as with any other signal generated by setting the port through GPIO.

 

In any case, there's no point in further guessing. Only a TI engineer can check your observations against the real silicon blueprints and explain what's going on.

Jens-Michael Gross said:

[Anyway, since the P1SEL.3 selects a signnal which is routed through the normal digital output, it shouldn't come with a slowly raising edge. The edges should be as steep as with any other signal generated by setting the port through GPIO.

That's the key! Further investigation of toggling P1.3 as a GPIO resulted in showing the same thing as the ADC10CLK output signal. I'm using the LaunchPad board and it has a 0.1uF capacitor to ground and a 47K resistor to VCC on P1.3. The drive output of the MSP430 cannot drive that RC load above a few 10's of Khz without major signal distortion and above 100Khz or so, the signal is no longer visible on the output pin.

So, that leads me to believe, as you stated, that the ADC10CLK output drive specs are the same as for general GPIO output.

Isolating the P1.3 pin from the LaunchPad board's RC components allowed me to now see the expected ADC10CLK output signal with any clock source (ACLK, MCLK, or SMCLK) and with any ADC10DIV divider setting.

Issue resolved/understood!

Thanks.

Dan K said:

I'm using the LaunchPad board and it has a 0.1uF capacitor to ground and a 47K resistor to VCC on P1.3.

Yes, that's of course applying a heavy load onto the port pin at teh beginning of the signal edges.
In a different thread, where the problem was a wrong output of the reference voltage to the P1.1..P1.3 pins, I already pointed out that P1.3 will behave differently due to the capacitor and the pullup. But I didn't connect this with your problem (maybe because the term 'LaunchPad' was not used in this thread before. And since I don't use any of these myself, I look only at the device type and (usually) don't notice in which EXP board or so they are (or vice versa)

Dan K said:

Isolating the P1.3 pin from the LaunchPad board's RC components allowed me to now see the expected ADC10CLK output signal with any clock source (ACLK, MCLK, or SMCLK) and with any ADC10DIV divider setting.

Hmmm, I wonder why you didn't the MCLK/SMCLK based ADC10CLK but the ACLK based one (or was teh ACLK significantly slower?)

Anyway, since it now turns out that indeed ADC10CLK is output to the P1. pin, the diagram for the P1.3 pin is wrong in the datasheet, as it shows ACLK as 'module output signal' and not ADC10CLK. Also, the fact that the signal is not symmetrical if an ADC10CLK divider is used, should be added somewhere. YOu already filed a bug report, you should file another one and gain you a reputation :)