Cannot see RTCCLK at ouput pin?

Praval,

Thank you for responding.  I guess I should have been more specific.  I'm sourcing RT0PS from ACLK, where ACLK is being sourced from REF0CLK at 32768 Hz.  I set RT0PS to divide ACLK by 256, and I set RT1PS to divide RT0PS by 128.  I also set RTC_A clock to be sourced by the output of RT1PS.  I did this even though TI says that it will happen automatically.  Furthermore, I set both the SEL bit and the DIR bit for P2.4.

The output frequency for RTCCLK at P2.4 can be selected as either no frequency output, 512 Hz, 256 Hz, or 1 Hz.  These choices are for measuring the frequency in order to calibrate the RTCCLK.  The frequency is selected using the RTCCALF bits in register RTCCTL3.  TI did note, however, that changes in the calibration settings will only be seen when using the 1 Hz option.

I initialized all of the undefined registers appropriately, and proceeded to clear the RTCHOLD bit in register RTCCTL1 in order to release the module for operation.  I have yet to see the clock at the output pin.

As of now I'm not really sure if the module turned on at all.  I plan on returning to it later after I do some other stuff.  I thought I might try to read one of the registers to see if it's being incremented, or to try to initiate a one minute interrupt and make the LED flash when this happens or something along those lines.

It's just a little frustrating when something like this happens when you believe to have followed the user manual.  I've also experienced XT1CLK not functioning properly when setup for LF operation.  I assumed that the MSP430F5438 has internal crystals for LF and HF operation, but I'm starting to second guess this assumption.  But then again, why would they have a select bit for internal or external sourcing?  I even tried TI's source code, as is, and I get the same result.  XT1LFOFFG can never stay cleared, and REF0 assumes the role in place of XT1CLK.

Anyway, thanks again for your response.  I hope that I've given you a better picture of what I've tried to do.

-Brian

Priya,

Thank you for clarifying that for me.  And yes, I do already have a TI target board, MSP-FET430UIF.  Why is it that the RTC cannot work off of the REF0 ?  Furthermore, for the loop that you provided, OFIFG will only be able to stay cleared when all oscillator faults do not exist, correct?  So if I'm not using XT2CLK, or if the DCO bits in the UCSCTL0 register are value {0} or {31}, then won't OFIFG stay set?  If so, wouldn't it make more sense to test (UCSCTL7 & XT1LFOFFG)?

Thanks again!

-Brian

Brian,

Semajmichael said:

Why is it that the RTC cannot work off of the REF0 ?

The RTC can absolutely work using the REFO as a clock source. I was only implying that if you are looking for precision (lower ppm error) an external 32KHz crystal maybe a better choice. If the REFO is sufficient for the needs of your application then you can definitely use it for RTC. Please refer to the device datasheet for REFO tolerance and drift specs.

Semajmichael said:

If so, wouldn't it make more sense to test (UCSCTL7 & XT1LFOFFG)?

I think the idea is that once the UCS is initialized as required, there should not be any faults. So the code examples tests (SFRIFG1&OFIFG) to ensure that there are no faults. This is a best practise and the recommended inittialization routine. It is upto the user to test fault flags as required.

Regards,

Priya

I also have some questions about using the RTCCLK output. I am trying to use the RTCCAL bits to compensate for the crystal freq drift over temperature.I am running your above example code so as to not confuse what I'm seeing with my code.

I have an HP 5385A Freq Counter which doesn't go down to 1Hz so I cleared the RTCCALF1 bit in order to measure 512Hz at the RTCCLK pin. I read 511.9965Hz. The counter reference freq is supplied by a precision GPS compensated source so I believe it to be stable and accurate. I compute that freq to be ~6.8PPS low so set RTCCALS and RTCCAL0 to correct it.

I then reset the RTCCALF1 bit to get a 1Hz output from RTCCLK and connect that to chan A on my Oscope. I connect the GPS clocks 1PPS signal to chan B on the scope and configure the scope to measure the delay time between the two inputs. I expected to see a fairly constant delay but see that there is a steady drift. I attempted to correct it by setting more RTCCALX bits but don't see a change in the delay time. I have tried setting and clearing RTCCALS with large RTCCAL values and still don't see a change in the delay time.

Am I missing something or is there something wrong with my test setup?

I also read in the Errata Sheet that the RTCCAL value can be off by 2PPS. Is there any way to work around this? I was hoping to be able to achieve finer compensation by by having a lookup table of calibration register values based on temperature. I had hoped to dither the register values between steps in order to get better than the available 2 to 4  PPM resolution. If the actual correction has a random 2PPM error then my idea will not work.

After looking more closely I see that RTCCAL5 and RTCCAL4 do correctly cause discrete freq steps approximately every 30 secs. I can change the step direction with RTCCALS. However I cannot get any effect with the four lower bits RTCCAL3 - RTCCAL0. I see the correct bits set in memory at 0x04A2. It appears to me to be a problem in the processor. Anyone else experience problems like this?

I am trying to get RTCCLK for F5529 -

  made the following changes to existing UCS7 code:

1. Set up P2.6 as output for RTCCLK.

2. Set up RTCCTL23 to 0x01 to output 512 Hz signal.

3. Added RTC_A configuration & start.

I am getting RTC to update - viewing RTC registers in Debug mode.

I am seeing all 3 clocks on appropriate pins: 32 KHz, 1 MHz (DCO) and 4 MHz (XT2).

However, I am not seeing the 512 Hz signal on pin 36 (P2.6) - any help?

I just noticed that the 5529 part that came with the MSP-TS430PN80USB board is an "x430F5529, REV A."

If I were to procure a more recent part, would that allow me to see RTCCLK?

Does anyone have experience of looking at the RTCCLK on the MSP-TS430PN80USB board?

I found the problem - I was setting up the wrong value for RTCCTL23 - needed to be a value of 0x0100 to enable RTCCLK out on P2.6.

> Am I missing something or is there something wrong with my test setup?

SA: It is not easy to see the effect of calibration if your calibration value is small. You may need to wait up to 64 minutes to see if it actually works or not. What the reference manual says: