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Integer division by zero

Francisco Torres
Intellectual 585 points


Hello,

In register "c1, System Control Register" bit 19

[19] DZ Divide by zero:

0 = do not generate an Undefined instruction exception
1 = generate an Undefined instruction exception.
The reset value of this bit is 0.

I would like to change this value to 1, so an undefined instruction exception is generated. The question is:

How can I know if the reason of the undefined instruction exception is a division by zero or any other cause?

In the "ARM Architecture Reference Manual" I can read

"The only mechanism to determine the cause of an Undefined Instruction exception is analysis of the instruction indicated by the return link in the LR on exception entry. Therefore it is important that a coprocessor only reports exceptional conditions by generating Undefined Instruction exceptions on its own coprocessor instructions."

So, I guess that the only way of knowing if the undefined instruction exception was caused by a division by zero is to check if LR points to a either UDIV or SDIV instructions and divisor is 0.

Is there an easier way to know if the undefined instruction exception was caused by a division by zero?

Thanks for helping.

Francis.

  • 0
    TI__Genius 11645 points
    Hello Francis,

    Do not have an answer ready on this, I need to check and get back to you on this to see if there is a better way out.
  • 0 in reply to KARTHIKEYAN RAJAMANICKAM
    TI__Expert 6985 points
    Hi Francis,

    The following is copied from the ARMv7-R Architecture Manual:

    Note
    The only mechanism to determine the cause of an Undefined Instruction exception is analysis of the instruction indicated by the return link in the LR on exception entry.

    Best Regards,
    Christian
  • 0 in reply to Christian Herget
    Intellectual 585 points

    Hello Christian,

    Yes, I saw this comment. As this can be quite complicated I was just asking if by any change there is any other  way, I will assume no.

    Thanks for helping.

    Francis.

  • 0 in reply to Francisco Torres
    TI__Expert 6985 points

    Hi Francis,

    Sorry, I missed that you copied exactly the same from ARM.

    Please keep in mind, that an Undefined Instruction Exception is usually indicating a very severe issue.
    What I want to say with this is, what's the value of knowing the instruction which caused the Exception, except for debugging purpose?

    If you like to do so you should take a look into:

    The Example (47) code to determine the address of the instruction caused the SVC should be similar to the one needed for UNDEF as:

    Best Regards,
    Christian

  • 0 in reply to Christian Herget
    Intellectual 585 points
    Hello Christian,

    "What's the value of knowing the instruction which caused the Exception, except for debugging purpose?"

    We want to enable in register "c1, System Control Register" bit [19] DZ Divide by zero:
    0 = do not generate an Undefined instruction exception
    1 = generate an Undefined instruction exception.
    The reset value of this bit is 0.

    So, when I set this bit to 1, a division by zero (I mean integer division, float division are handled by the FPU and we already have that covered), so division by zero will generate an undefined exception. We would like to signal that to the user but without stopping the execution. As you pointed an undefined exception is very serious and at the moment we go to safe state.

    So, by enabling this, we would like to inform the user that something is wrong in his/her code but continue with the execution.

    Regards,
    Francis.