CPU Register Initialization

Dmitri Zakharevski59

Other Parts Discussed in Thread: HALCOGEN

Hello,

I have a question about CPU Register initialization for the RM57 chip.
In section 5.5.4.3 of http://www.ti.com/lit/ds/symlink/rm57l843.pdf

bl    $+4
bl    $+4
bl    $+4
bl    $+4
bx    r0

It also appears in Halcogen generated code as

bl    next1
next1
        bl    next2
next2
        bl    next3
next3
        bl    next4
next4
        bx    r0

Could you explain what this section of code does? I cant find any more documentation around it in either the ARM or TI documents.

Thanks!

Dmitri

over 10 years ago

0 Zhaohong Zhang over 10 years ago

TI__Mastermind 22715 points

They are doing the same thing: branch to the address of the next instruction.

Thanks and regards,

Zhaohong

0 Dmitri Zakharevski59 over 10 years ago in reply to Zhaohong Zhang

Intellectual 905 points

Hi Zhaohong,

Thank you for the reply, but this does not answer my question. I am trying to understand why they are branching, what is the purpose/intent of the code.

Thanks!

Dmitri

0 Zhaohong Zhang over 10 years ago in reply to Dmitri Zakharevski59

TI__Mastermind 22715 points

The purpose of those branches is to add some time delay.

Thanks and regards,

Zhaohong

0 Sunil Oak over 10 years ago in reply to Zhaohong Zhang

TI__Mastermind 49120 points

Dmitri, Zhaohong,

That is not correct. These four instructions are for initializing the call-return stack, which consists of a 4-entry circular buffer (hence the four branches). Please refer to the Cortex R4F TRM version r1p3 page 210, section 5.3 "Return Stack".

0 Anthony F. Seely over 9 years ago in reply to Sunil Oak

TI__Guru 68970 points

Dmitri,

Rationale for this is given in www.ti.com/.../getliterature.tsp
Section 2.2. "A core compare module (CCM-R4) compares the output signals from each R4F CPU. Any
difference in the two CPUs’ outputs is flagged as a fault of a high-severity level. "

These call stack registers are additional uninitialized registers just like r0-r15 except that you cannot write to them directly. The only way to initialize them to the same state is to take the branches.

This application report is for the Cortex R4F but in this case it also applies to the Cortex R5F.

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CPU Register Initialization