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Tiva TM4C-129X (DK), OpenOCD

Other Parts Discussed in Thread: TM4C129ENCPDT, SEGGER

Hi guys,

I'm new user of Tiva 129x, now I;m trying to flash this board via OpenOCD, but I always get problem.

I downloaded new patch from OpenOCD.org for TIVA TM4C-129x. Compilation driver is ok.

But when I configure my .cfg file to download binary, the reset_config is problem. 

When I used this command or related command to reset TIVA, I got the message error: JTAG-DP STICKY ERROR.

I suggested there are any problem with registers. I tried to configure but no success.

It's new cortex-m4 from TI, have you anyone experience with this platform?

Thank you for any help.

  • Hello Quang,

    1. Which DK or EK board are you using or is it a custom board?

    2. What is the cfg file you are using. Can you please attach the same?

    3. What is the Emulator HW you are using?

    4. Which version of OPENOCD is this?

    Regards

    Amit

  • Hi Amit,

    1. Sorry I'm wrong. It's my customer kit based on platform TM4C129ENCPDT with ecternal OSC. 25Mhz.

    2. Attached You will find the .cfg files

    3. I'm using emulator from J-link SEGGER USB-JTAG, the black one.

    4. OpenOCD version 0.8 - dev.

    I think I'm wrong in config for registers, can you check them?

     Thank you,

    Quang

    tm4c129.cfg
  • PS: I attached the second .cfg file

    Quang

    3su1.cfg
  • In the second cfg file did you try to use

    flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME

    instead of

    flash bank $_FLASHNAME tiva 0 0 0 0 $_TARGETNAME

    Also it would be good if you can send the output from OPENOCD when you try to connect?

    Regards

    Amit

  • I tried it but no succes. Here is my output on terminal.

     

    openocd -s /openocd/ -f 3su1.cfg -c "init;halt;reset init;sleep 1000;flash probe 0;flash write_image erase 3su1_led.elf;sleep 100;resume;shutdown"

    Open On-Chip Debugger 0.8.0-dev-00382-g1262f9b-dirty (2014-03-17-15:46)
    Licensed under GNU GPL v2
    For bug reports, read
    http://openocd.sourceforge.net/doc/doxygen/bugs.html
    Info : only one transport option; autoselect 'jtag'
    adapter speed: 500 kHz
    srst_only separate srst_gates_jtag srst_open_drain connect_deassert_srst
    adapter_nsrst_delay: 100
    TapName Enabled IdCode Expected IrLen IrCap IrMask
    -- ------------------- -------- ---------- ---------- ----- ----- ------
    0 TM4C129ENCPDT.cpu Y 0x00000000 0x4ba00477 4 0x01 0x0f
    Info : J-Link initialization started / target CPU reset initiated
    Info : J-Link ARM V8 compiled Dec 1 2009 11:42:48
    Info : J-Link caps 0xb9ff7bbf
    Info : J-Link hw version 80000
    Info : J-Link hw type J-Link
    Info : J-Link max mem block 9576
    Info : J-Link configuration
    Info : USB-Address: 0x0
    Info : Kickstart power on JTAG-pin 19: 0x0
    Info : Vref = 3.248 TCK = 1 TDI = 0 TDO = 1 TMS = 0 SRST = 0 TRST = 0
    Info : J-Link JTAG Interface ready
    Info : clock speed 500 kHz
    Info : JTAG tap: TM4C129ENCPDT.cpu tap/device found: 0x4ba00477 (mfg: 0x23b, part: 0xba00, ver: 0x4)
    Info : TM4C129ENCPDT.cpu: hardware has 6 breakpoints, 4 watchpoints
    target state: halted
    target halted due to debug-request, current mode: Thread
    xPSR: 0x81000000 pc: 0x000004b8 msp: 0x200000ec
    Info : JTAG tap: TM4C129ENCPDT.cpu tap/device found: 0x4ba00477 (mfg: 0x23b, part: 0xba00, ver: 0x4)
    Error: JTAG-DP STICKY ERROR
    Error: MEM_AP_CSW 0x23000040, MEM_AP_TAR 0x0
    Error: timed out while waiting for target halted
    TARGET: TM4C129ENCPDT.cpu - Not halted

    in procedure 'reset'
    make: *** [load] Error 1

    Thanks,

    Quang

  • Hello Quang,

    Looking at the logs

    target state: halted
    target halted due to debug-request, current mode: Thread
    xPSR: 0x81000000 pc: 0x000004b8 msp: 0x200000ec

    it seems that there is already some code that has been loaded. It could be possible that the code is preventing a successful JTAG connection. Can you let me know what is that was already loaded. The OPENOCD connection the first time around should have worked after which you have been facing this issue.

    Regards

    Amit

  • Hello Amit,

    Yes, you are right in it. First time I load my binary to target, it was successful. But the MCU didn't reset. I have to remove power and plugin again. Here is my output on termianl WITHOUT RESET_CONFIG. To write to flash I use:

    flash write_image erase 3su1.elf.

    Here is my output:

    TI Tiva information: Chip is class 10 (Tiva-Snowflake) TM4C129ENCPDT rev A0
    did1: 0x102dc06c, arch: 0x102dc06c, eproc: ARMv7M, ramsize: 256k, flashsize: 1024k
    pagesize: 16384, pages: 64, lockbits: 64, pages per lockbit: 1

    init_mcu
    enable peripherals
    PLLA = 480MHz, MCK = 48 MHz (3 Flash Wait State cycles)
    adapter speed: 6000 kHz
    3SU1 Initialized
    Blink LEDs twice
    flash 'tiva' found at 0x00000000
    auto erase enabled
    Warn : function tiva_set_flash_timing is not implemented, MEMTIM0 should be set here
    Warn : current value of MEMTIM0 = 0xc300c3
    Warn : function tiva_set_flash_timing is not implemented, MEMTIM0 should be set here
    Warn : current value of MEMTIM0 = 0xc300c3
    wrote 16384 bytes from file 3su1_led.elf in 0.245165s (65.262 KiB/s)
    shutdown command invoked

     

    But when I use reset_config, I got the ERROR as you see above. Where I'm wrong?

    Thanks,

    Quang

  • Hello Quang,

    So the first time when the MCU did not reset, you added this statement. Is that correct?

    After adding this statement it started giving an error. Is that correct?

    Now when the SRST is asserted assuming that reset from J-LINK is connected to the RST_N Pin of the device, the device will re-start. The Debugger will also try to reconnect in the meantime causing Fault to appear and since a halt is not issued it will not halt the core causing it to break. Can you add "halt" as part of the load routine.

    openocd -s /openocd/ -f 3su1.cfg -c "init; reset init; sleep 1000; halt; flash probe 0;flash write_image erase 3su1_led.elf;sleep 100;resume;shutdown"

    Regards

    Amit

    Please also note that reset_config affects the way reset is given to the device.

    http://openocd.sourceforge.net/doc/html/Reset-Configuration.html#srstandtrstissues

  • Hello Amit,

    After adding this statement it started giving an error. Is that correct? --> exactly!

    openocd -s /openocd/ -f 3su1.cfg -c "init; reset init; sleep 1000; halt; flash probe 0;flash write_image erase 3su1_led.elf;sleep 100;resume;shutdown" 

    -> no success. I can load my .elf without ERROT but without reset_config. After loading, I have remove power to reset MCU.

    Now, I use JTAG-KEY 2 from AMONTEC, no changed. About NST_N pin, I will check and give you the feedback. 

     

     

     

     

     

     

     

  • Hello Quang

    What is the error you are getting?

    Regards

    Amit

  • PS: RST_N pin. Sorry

  • Hello Amit,

    I have checked the design of board. Yes, JTAG SRTS is connected to RST_N pin on the MCU. I have checked by OSCI to. There is really the voltage  changes from 3.3V to 0V to reset. But after that it's error message:

    ERROR: JTAG-DP STICKY ERROR

    ERROR: MEM_AP CSW 0x23....

    TARGET: TM4C...cpu - Not halted.

    Quang

  • Hello Quang,

    I moved the reset init after loading the code and the new code now works for me,

    openocd -s /openocd/ -f 3su1.cfg -c "init;halt;flash probe 0;flash write_image erase 3su1_led.elf;sleep 100;reset init ;shutdown"

    Please note I am using FTDI drivers and not JLINK but the issue as you mentioned exists for FTDI interface also.

    Regards

    Amit

  • Hello Amit,

    can you send your all .cfgs files to me? Better to email: hquangcvut@yahoo.com

    Thank you,

    Quang

  • Hello Quang,

    I am on a 0.7.0 release build of OPENOCD and am using Stellaris style drivers. But this is a known issue on OPENOCD as a lot of folks have encountered this

    Regards

    Amit