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TM4C129x GPIO APB vs AHB

Randy Ott
Intellectual 750 points
Other Parts Discussed in Thread: TM4C1294NCPDT

I am in the process of porting some TM4C123x code to the '129. I am using driver libraries from TivaWare version 2.1.0.12573.

I notice that when I call this function : GPIOPinConfigure(GPIO_PA2_T1CCP0) which is used to configure the port pin to be used as the timer compare output, the constant "GPIO_PA2_T1CCCP0" refers to the APB base address of the port instead of the AHB base address.

According to the '129 data sheet, the GPIO ports do not connect to the APB, only AHB connections are shown.

If I watch the registers in the debugger, the port seems to be affected but the base addresses are different.

I believe the whole issue is because the GPIO_PA2_T1CCCP0 constants that are defined in pin_map.h do not have provisions to support AHB addresses on the '129 parts.

Perhaps this will be fixed in later versions but I'm still not sure why the code works unless there is some undisclosed compatibility mode going on in the silicon.

Randy

  • TI__Guru**** 244400 points

    Hello Randy,

    In the GPIOPinConfigure function based on whether the GPIOHBCTL register bit is set or not the AHB or APB address space is taken respectively. Now the APB address aperture does exist but this is a transition from APB to AHB and is provided for any issue on TM4C129. That is why you can still some of the peripherals from APB Address aperture.

    Regards

    Amit

  • in reply to Amit Ashara
    Intellectual 750 points

    OK, thanks for the info.  I see how this works on the '123x devices but the GPIOHBCTL register is no where to be found in the TM4C1294NCPDT data sheet.

    All of the example projects for the '129x in TivaWare still use the APB to access the ports.

    I have to assume that the '129x parts still have both APB and AHB connections to the ports but this is just not documented.

    Randy

  • in reply to Randy Ott
    TI__Guru**** 244400 points

    Hello Randy

    Since we have moved it completely to AHB, the register is now hard coded for AHB Bus Access. Since AHB is more efficient in sending data to the GPIO then APB, we do not any longer document it

    Regards

    Amit

  • in reply to Amit Ashara
    Intellectual 750 points

    One more thing, just to be sure I understand this.

    If I write to an address referenced to the GPIO_PORTA_BASE which is 0x40004000, does the hardware actually route this to 0x40058000 which is the GPIO_PORTA_AHB_BASE address?

    If so, will this behavior be the same on all of the current '129x parts and future revisions?

    Is this why the old '123x example code works on the '129x?

    Randy

  • in reply to Randy Ott
    TI__Guru**** 244400 points

    Hello Randy,

    Going forward AHB will be the bus of choice, so I don't think that the APB bus will exist anymore. Eventually this may lead an application to Bus Fault. Hence the GPIOHBCTL exists to auto map that for the moment.

    Regards

    Amit

  • in reply to Amit Ashara
    Intellectual 750 points

    Yes, I get that.

    I'm just concerned about writing code that works on the existing hardware due to some undocumented features that will break somewhere down the road.

    Randy

  • in reply to Randy Ott
    TI__Guru**** 244400 points

    Hello Randy

    I understand. We will try to keep it least disruptive when it comes to the next device.

    Regards

    Amit