I am using the IAR EWARM IDE and a TM4C129EKCPDT processor. I am trying to figure out how to clear the DBG1 bit in the BOOTCFG register so as to disable the JTAG interface.
The datasheet for the chip says that the BOOTCFG register is at offset 0x1DE from the System Control base address (0x400f.e000), and that the default value of the register contents should be 0xffff.fffe (DBG0 gets cleared by factory).
I used the following code to read the value of BOOTCFG:
U32 *bootCfPtr = (U32*)(SYSCTL_BASE + 0x01deU);
U32 bootCfgReg = *bootCfgPtr;
However, the value reported is 0xffff.ffff, not 0xffff.fffe, which makes me wonder whether I am reading the correct register. Unfortunately, the IAR debugger does not seem to support reading the BOOTCFG register, so I have nothing to compare to.
Am I doing this right, and if so, why would I not be getting the expected register contents?
Also, I am confused about what address to write to when changing BOOTCFG. Table 8.3 says to set the FMA register to 0x7510.000 to program BOOTCFG. Why wouldn’t this address be 0x400f.e1de?
One last thing. Once I get the above sorted out, I was planning on using the TivaWare FlashProgram() function to change the register:
FlashProgram(bootCfgReg, (U32*)0x75100000, 4);
Will that work?
Thanks,
Dave
