CCS: RM46L852 LAUNCHPAD AND DP83640 PHY

Shruthi Gurunath66

Part Number: RM46L852
Other Parts Discussed in Thread: HALCOGEN, DP83640,

Tool/software: Code Composer Studio

Hi Team,

I want to communicate through EMAC to PHY. I have used the code available as Loopback in Halcogen, with loopback it is working fine. But whenever I send the packets, TX_EN is not getting higj. TX_CLK and RX_CLK are coming properly. I have not connected any DHCP/UDP. Please suggest the answers.

over 6 years ago

0 Shruthi Gurunath66 over 6 years ago

Intellectual 360 points

Tool/software: Code Composer Studio

Hi I am not recieving any answers.

0 Miro over 6 years ago

TI__Mastermind 21425 points

Hello,
PLease check whether your PINMUX setting were set according to Table 32-4. MII/RMII Multiplexing Control .

Best regards,
Miro

0 Shruthi Gurunath66 over 6 years ago in reply to Miro

Intellectual 360 points

Yes, I have set and checked in the PINMMR for MII and MDIO signals. My requirement is I have siemens with profinet interface. I want RM46L582 launch pad and DP83640 together send the packets to drive for setting or getting the parameters. Since HDK I am not using, according to HDK schematics only we connected DP83640 separately and I could able to write/read through DP83640 registers. Also 25MHz crystal I added. Loopback is working fine, but without loopback it is not at all working. TX_EN and TXD[3:0] stays at low itself. Please suggest, I am new to this ethernet.

0 Miro over 6 years ago in reply to Shruthi Gurunath66

TI__Mastermind 21425 points

Hello,
Please, check whether TXCLK is coming to MCU.

Best regards,
MIro

0 Shruthi Gurunath66 over 6 years ago in reply to Miro

Intellectual 360 points

Hello Miroslav Deyanov,

TXCLK is coming out from DP83640, but frequency is not proper. It is 6.25MHz. Please suggest the settings of DP83640 also. Please send any pseudocode is there.

I want to know whether EMAC packets and Siemens drives can be talk to each other through profinet bus.

0 Miro over 6 years ago in reply to Shruthi Gurunath66

TI__Mastermind 21425 points

Hello,
from here: processors.wiki.ti.com/.../HALCoGen_Ethernet_Driver_and_lwIP_Integration_Demonstration you can download APIs for configuring DP83640.

I am moving this thread to Interface forum for more details on DP83640 configuration.

Best regards,
Miro

0 Hung Nguyen92 over 6 years ago in reply to Miro

TI__Expert 5670 points

Hello,

Please make sure the DP83640 is in MII mode. Can you read out register 0x17?

In MII mode, both RX_CLK and TX_CLK are from the PHY. What do you see on RX_CLK?

Regards,

Hung Nguyen

0 Shruthi Gurunath66 over 6 years ago in reply to Hung Nguyen92

Intellectual 360 points

Registers of DP83640 are in MII Mode. TX_CLK and RX_CLK are 2.5MHz. But TX_EN is not coming at all.

I have a doubt whether I can to drives which has profinet interface.

0 Hung Nguyen92 over 6 years ago in reply to Shruthi Gurunath66

TI__Expert 5670 points

Hi Shruthi,

TX_EN is not driven by DP83640. It is coming from the EMAC.

Please make sure you configure the EMAC correctly or get support from processor team.

Regards,

Hung Nguyen

0 Shruthi Gurunath66 over 6 years ago in reply to Hung Nguyen92

Intellectual 360 points

Hi Hung,

Still problem is there. I am not able to see TXEn getting high through scope. I am able to see in the memory location. But ohysically in the scope it is not.

0 Shruthi Gurunath66 over 6 years ago

Intellectual 360 points

Part Number: RM46L852

Tool/software: Code Composer Studio

Hi Team,

Please tell us EMAC setting. I am using RM46L852 launchpad and DP83640 . connection similar to HDK. I am able to see the transmitted bytes in memory location. But physically through scope., it is not. Neither TXEN is seen nor other TXD. Please suggest

0 QJ Wang over 6 years ago in reply to Shruthi Gurunath66

TI__Guru**** 196296 points

Hello,

You said your loopback test passed. Is it EMAC internal loopback, or PHY internal loopback, or external loopback? External loopback is TXed data is looped back to RX at RJ45 connector.

To use MII, please pull-down RX_DV pin. The DP83640 provides five PHY address pins. The address pins are COL and RXD[3:0]. COL has weak internal pullup resistor, and RXD[3:1] have weak internal pulldown resistor. Since RXD[3:2] on TMS570 device have internal pullup resistor which is conflict with DP83640 internal pulls, please add a strong 2.2kohm pulldown resistor to RXD[3:2] signals.

Same thing for signal CRS, so please add a strong pullup resistor to CRS signal too.

The ethernet signal is high speed, using blue wires for the signals may not make them work since bad signal integrity.

0 Shruthi Gurunath66 over 6 years ago in reply to QJ Wang

Intellectual 360 points

Hi Wang,

It is PHY internal loopback,. I have set the bit in the DP83640.Other pull-down registers are already connected as you recommended. I changed the channel no.1 TXD is working, but RXD is not coming out of PHY. I could able to see RX_CLK and RX1HDP with 0xFC521010 but data is not there in buffer pointer.

0 QJ Wang over 6 years ago in reply to Shruthi Gurunath66

TI__Guru**** 196296 points

Hello,

Can you try external loopback? You need a ethernet adaptor to route TX back to RX.

/* ---------------------------------------------------------------- *
* Init PHY / MDIO *
* ---------------------------------------------------------------- */
MDIO_CONTROL = 0x41000020; // Enable MII interface 0x40000001
MDIO_USERACCESS0 = 0 // Read Phy Id 1
| ( 1 << 31 ) // [31] Go
| ( 0 << 30 ) // [30] Read
| ( 0 << 29 ) // [29] Ack
| ( 2 << 21 ) // [25-21] PHY register address
| ( 1 << 16 ) // [20-16] PHY address
| ( 0 << 0 ); // [15-0] Data

while( MDIO_USERACCESS0 & 0x80000000 ); // Wait for Results
phy_ctrl_reg = 0
| ( 0 << 15 ) // Reset
| ( 0 << 14 ) // Loopback
| ( 1 << 13 ) // Speed Selection
| ( 1 << 12 ) // Auto-Negotiation Enable
| ( 0 << 11 ) // Power-Down
| ( 0 << 10 ) // Isolate
| ( 0 << 9 ) // Restart Auto-Negotiation
| ( 1 << 8 ) // Duplex Mode
| ( 0 << 7 ) // Collision Test
| ( 0 << 6 ); // Speed Selection

MDIO_USERACCESS0 = 0 // Set Control Reg
| ( 1 << 31 ) // [31] Go
| ( 1 << 30 ) // [30] Write
| ( 0 << 29 ) // [29] Ack
| ( 0 << 21 ) // [25-21] PHY register address
| ( 1 << 16 ) // [20-16] PHY address
| ( phy_ctrl_reg << 0 ); // [15-0] Data

while( MDIO_USERACCESS0 & 0x80000000 ); // Wait for Results

// Waiting for link...
while( (phy_getReg( 1, 1 ) & 0x4 ) == 0) ;

/* ------------------------------------------------------------------------ *
* phy_getReg( phynum, regnum ) *
* ------------------------------------------------------------------------ */
uint16_t phy_getReg( uint16_t phynum, uint16_t regnum )
{
uint16_t value;

MDIO_USERACCESS0 = 0 // Read Phy Id 1
| ( 1 << 31 ) // [31] Go
| ( 0 << 30 ) // [30] Read
| ( 0 << 29 ) // [29] Ack
| ( (regnum & 0x1F) << 21 ) // [25-21] PHY register address
| ( (phynum & 0x1F) << 16 ) // [20-16] PHY address
| ( 0 << 0 ); // [15-0] Data

while( MDIO_USERACCESS0 & 0x80000000 ); // Wait for Results

value = MDIO_USERACCESS0;
return value;
}

0 QJ Wang over 6 years ago in reply to QJ Wang

TI__Guru**** 196296 points

This is my test code used before. Hope this helpful to you. This code follows the initialization steps listed in TRM.

/*
* 0. Reset Ethernet
*/
EMAC_SOFTRESET = 1;
while( EMAC_SOFTRESET != 0 );

/*
* 1. clear the device interrupt enable bits in the EMAC control module interrupt control registers
*/
ECTRL_C0RXEN = 0x00000000;
ECTRL_C0TXEN = 0x00000000;

/*
* 2. Clear the MAC control, receive control, & transmit control registers.
*/
EMAC_MACCONTROL = 0;
EMAC_RXCONTROL = 0;
EMAC_TXCONTROL = 0;

/*
* 3. Initialize all 16 header descriptor pointers RXnHDP & TXnHDP to zero
*/
pReg = &EMAC_RX0HDP;
for ( i = 0 ; i < 8 ; i++ )
*pReg++ = 0;

pReg = &EMAC_TX0HDP;
for ( i = 0 ; i < 8 ; i++ )
*pReg++ = 0;

/*
* 4. Clear all 36 statistics registers by writing 0
*/
pReg = &EMAC_RXGOODFRAMES;
for ( i = 0 ; i < 36 ; i++ )
*pReg++ = 0;

/*
* 5. Setup the local Ethernet MAC address by programming the MAC index register (MACINDEX), MAC
* address high bytes register (MACADDRHI), and MAC address low bytes register (MACADDRLO).
* Be sure to program all 8 MAC addresses- whether the receive channel is to be enabled or not.
*/
EMAC_MACINDEX = 0x00;
EMAC_MACADDRHI = 0x03020100; // Needs to be written only the first time
EMAC_MACADDRLO = 0x00180504;

EMAC_MACINDEX = 0x01;
EMAC_MACADDRLO = 0x1504;

EMAC_MACINDEX = 0x02;
EMAC_MACADDRLO = 0x2504;

EMAC_MACINDEX = 0x03;
EMAC_MACADDRLO = 0x3504;

EMAC_MACINDEX = 0x04;
EMAC_MACADDRLO = 0x4504;

EMAC_MACINDEX = 0x05;
EMAC_MACADDRLO = 0x5504;

EMAC_MACINDEX = 0x06;
EMAC_MACADDRLO = 0x6504;

EMAC_MACINDEX = 0x07;
EMAC_MACADDRLO = 0x7504;

/*
* 6. Initialize the receive channel N free buffer count registers(RXnFREEBUFFER), receive channel n flow control threshold register (RXnFLOWTHRESH),
* and receive filter low priority frame threshold register (RXFILTERLOWTHRESH).
* I don't use this since I disabled the buffer flow control
*/

/*
* 7. No multicast addressing, so clear the MAC address hash registers (MACHASH1 and MACHASH2) to 0.
*/
EMAC_MACHASH1 = 0;
EMAC_MACHASH2 = 0;

/*
* 8. Set RX buffer offset to 0
* Valid data always begins on the 1st byte
*/
EMAC_RXBUFFEROFFSET = 0;

/*
* 9. Enable Unicast RX on channel 0-7
*/
EMAC_RXUNICASTSET = 0xFF;

/*
* 10. Setup the RX( M )ulticast ( B )roadcast ( P )romiscuous channel
*/
EMAC_RXMBPENABLE = 0x01e02020;

/*
* 11. Set the appropriate configuration bits in MACCONTROL (do not set the GMIIEN bit yet).
*/
EMAC_MACCONTROL = 0
| ( 1 << 15 ) // 100MHz RMII
| ( 0 << 9 ) // Round robin
| ( 0 << 6 ) // TX pacing disabled
| ( 0 << 5 ) // GMII RX & TX
| ( 0 << 4 ) // TX flow disabled
| ( 0 << 3 ) // RX flow disabled
| ( 0 << 1 ) // Loopback disabled
| ( 1 << 0 ); // full duplex

/*
* 12. Clear all unused channel interrupt bits by writing the receive interrupt mask clear register
*/
EMAC_RXINTMASKCLEAR = 0xFF;
EMAC_TXINTMASKCLEAR = 0xFF;

/*
* 13. Enable the RX & TX channel interrupt bits in the receive interrupt mask set register (RXINTMASKSET)
* and the transmit interrupt mask set register (TXINTMASKSET) for the channels to be used, and enable the HOSTMASK and STATMASK bits
* using the MAC interrupt mask set register (MACINTMASKSET).
*/
EMAC_RXINTMASKSET = 0xFF;
EMAC_TXINTMASKSET = 0xFF;

/* Enable Host Error and Statistics interrupts */
EMAC_MACINTMASKSET = 0
| ( 1 << 1 ) // Host Error interrupt mask
| ( 1 << 0 ); // Statistics interrupt mask

/*
* 14. Initialize the receive and transmit descriptor list queues.
*/

/*
* 15. Prepare receive by writing a pointer to the head of the receive buffer descriptor list to RXnHDP.
*/

EMAC_MACSRCADDRLO = 0x00180504; /* bytes 0, 1 */
EMAC_MACSRCADDRHI = 0x03020100; /* bytes 2-5 - channel 0 ??? */
// EMAC_MACSRCADDRLO = 0x03020100; /* bytes 0, 1 */
// EMAC_MACSRCADDRHI = 0x0405; /* bytes 2-5 - channel 0 ??? */

/*
* 16. Enable the RX & TX DMA controllers.
* Then set GMIIEN
*/
EMAC_RXCONTROL = 1;
EMAC_TXCONTROL = 1;
EMAC_MACCONTROL |= ( 1 << 5 );

/* 17. Enable the device interrupt in EWCTL. */
ECTRL_C0RXEN = 0x00000001;
ECTRL_C0TXEN = 0x00000001;

0 Shruthi Gurunath66 over 6 years ago in reply to QJ Wang

Intellectual 360 points

sys_main.c

/** @example example_EMAC_Loopback_TxRx.c
* This is an example which describes the steps to create an example application which
* uses the HALCoGen driver to send and receive broadcast Ethernet packets in loopback mode.
* The EMACTransmit API is used for transmitting a single packet. Here, it is called twice, thereby transferring two packets.
* To see the transmitted information, the transmitted and receive buffer descriptors must be observed, which are located in the EMAC RAM.
* In the default configuration, the transmitted descriptors can be found at 0xFC520000 (Base address of EMAC RAM) and the receive descriptors start at 0xFC521010.
* One can also observe the number of packets transmitted and other such information in the EMAC network statistics registers.
*
* @b Step @b 1:
*
* Create a new project.
*
* Navigate: -> File -> New -> Project
*
* @image html example_createProject.jpg "Figure: Create a new Project"
*
* @b Step @b 2:
*
* Configure driver code generation:
* - Enable EMAC driver
* - Disable others
*
* Navigate: -> TMS570LSxx /RM4 -> Driver Enable
*
* @image html example_freeRTOSBlinky_enableDrivers_TMS570LS3x-RMx.jpg "Figure: Driver Configuration"
*
* @b Step @b 3:
*
* Configure Interrupt handling:
* - Under ‘VIM Channels 64-95’, enable EMAC Tx and Rx interrupts (Channels 77 and 79 respectively).
*
* Navigate: -> TMS570LSxx /RM4 -> VIM Channels 64-95
*
* @image html emac_interruptenable.jpg "Figure: Interrupt Configuration"
*
* @b Step @b 4:
*
* Configure PLL:
* - Under the ‘PLL’ tab, change the multiplier for both PLLs to a value of 120, such that the output frequency in both cases is 160.00 MHz.
*
* Navigate: -> TMS570LSxx /RM4 -> PLL
*
* @image html emac_PLL.jpg "Figure: PLL Configuration"
*
* @b Step @b 5:
*
* Configure GCM:
* - Under the ‘GCM’ tab, change the value of the VCLKA4 Divider to 2,
*   such that the output of VCLKA4( or VCLKA4_DIVR_EMAC in case of RM46x/TMS570LS12x Devices) is 40.00 MHz.
*
* Navigate: -> TMS570LSxx /RM4 -> GCM
*
* @image html emac_gcm.jpg "Figure: GCM Configuration"
*
* @b Step @b 6:
*
* Configure PINMUX
* - Under the ‘PINMUX’ tab, enable RMII/MII, MDIO(G3) & MDCLK(V5).
*
* Navigate: -> OS -> PINMUX.
*
* @image html emac_pinmux.jpg "Figure: PINMUX Configuration"
*
* @b Step @b 7:
*
* Configure EMAC:
* -change the EMAC address to any MAC Address of your choice. The physical address is 1 by default.
* -Enable Loopback. Leave the other options with their default values.
* Navigate: -> File -> EMAC
*
* @image html emac_config.jpg "Figure: EMAC Configuration"
*
* @b Step @b 8:
*
* Generate code
*
* Navigate: -> File -> Generate Code
*
* @image html example_freeRTOS_generateCode.jpg "Figure: Generate Code"
*
* @b Step @b 9:
*
* Copy source code below into your application.
*
* The example file example_EMAC_Loopback_TxRx.c can also be found in the examples folder: ../HALCoGen/examples
*
* @note HALCoGen generates an empty main function in sys_main.c,
*        please make sure that you link in the right main function or copy the source into the user code sections of this file.
*
*/

#include "sys_common.h"
#include "system.h"
#include "sys_vim.h"

/* USER CODE BEGIN (1) */
#include "emac.h"
#include "hw_reg_access.h"
#include "pinmux.h"
/* USER CODE END */

/** @fn void main(void)
*   @brief Application main function
*   @note This function is empty by default.
*
*   This function is called after startup.
*   The user can use this function to implement the application.
*/

uint8   emacAddress[6U] =   {0x00U, 0x08U, 0xEEU, 0x03U, 0xA6U, 0x6CU};
uint32 emacPhyAddress =   1U;

/* USER CODE BEGIN (2) */
extern hdkif_t hdkif_data[1];
pbuf_t pack[5];
static uint8 data[5][1024];

uint32 size1 = 212,size2=106;
volatile uint16 DP83640_RMIIBYPASS, DP83640_BMCR;
volatile uint16 Test;
volatile uint16 TestTx, TestRx;
int i,j;

void create_packet()
{

    for(i=0;i<2;i++)
    {
    pack[i].tot_len = size1;
    pack[i].len = size2;
    for(j=0;j<7;j++)
    {
        data[i][j] = 0x55u;

    }

    data[i][7]= 0x5D;

    for(j=0;j<6;j++)
    {
        data[i][j+8]= emacAddress[j];
    }

    for(j=0;j<6;j++)
    {
       data[i][j+14]= emacAddress[j];
    }

    data[i][20] = 0x00;
    data[i][21] = 0x50;

    for(j=0;j<80;j++)
    {
        data[i][j+22] = i+5;
    }

    for(j=0;j<4;j++)
       {
           data[i][j+103] = i+5;
       }
   // pack[i].next= NULL;
    pack[i].payload = &data[i][0];
    if(i==0)
    pack[i].next = &pack[i+1];

    else
    pack[1].next= NULL;
    }
}
/* USER CODE END */

void main(void)
{
/* USER CODE BEGIN (3) */
    TestTx=0;
    TestRx=0;
    _enable_IRQ();
    EMACHWInit(emacAddress);
    HWREG(0xFCF78160) = 0x00000021;
    HWREG(0xFCF7816C) = 0x00020002;
    HWREG(0xFCF78500) = 0x00116CA6;
    HWREG(0xFCF78508) = 0x00000001;
    HWREG(0xFCF780B8) = 0x00000003;
    HWREG(0xFCF780B8) = 0x00000003;
    HWREG(0xFCF78100) = 0x01E12100;
    //HWREG(0xFCF78104) = 0x00000002;
    //HWREG(0xFCF78108) = 0x00000002;
    //HWREG(0xFCF7810C) = 0x000000BE;
    //HWREG(0xFCF78008)=0x01;
    //HWREG(0xFCF7808C) = 0x00;
    MDIOPhyRegWrite(0xFCF78900, 0x00000001, 0x00, 0x4100);
    MDIOPhyRegWrite(0xFCF78900, 0x00000001, 0x1B, 0x0040);
    MDIOPhyRegWrite(0xFCF78900, 0x00000001, 0x1C, 0x0000);
    MDIOPhyRegWrite(0xFCF78900, 0x00000001, 0x17, 0x0001);

    MDIOPhyRegWrite(0xFCF78900, 0x00000001, 0x00, 0x4100);
    MDIOPhyRegWrite(0xFCF78900, 0x00000001, 0x1B, 0x0040);
    MDIOPhyRegWrite(0xFCF78900, 0x00000001, 0x1C, 0x0000);
    MDIOPhyRegWrite(0xFCF78900, 0x00000001, 0x17, 0x0001);
    MDIOPhyRegRead(0xFCF78900, 0x00000001, 0x1C, 0x00);

    create_packet();

//    size1=600;
//    size2=120;
//    create_packet();
//    EMACTransmit(&hdkif_data[0], &pack[0]);

    while(1)
    {

        EMACTransmit(&hdkif_data[0], &pack[0]);
        for(i=0;i<10000;i++);

        EMACReceive(&hdkif_data[0]);
    }
/* USER CODE END */
}

Emac.c

/**
* \file   emac.c
*
* \brief EMAC APIs.
*
*   This file contains the device abstraction layer APIs for EMAC.
*/

/*
* Copyright (C) 2009-2016 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
*    Redistributions of source code must retain the above copyright
*    notice, this list of conditions and the following disclaimer.
*
*    Redistributions in binary form must reproduce the above copyright
*    notice, this list of conditions and the following disclaimer in the
*    documentation and/or other materials provided with the
*    distribution.
*
*    Neither the name of Texas Instruments Incorporated nor the names of
*    its contributors may be used to endorse or promote products derived
*    from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/

/* USER CODE BEGIN (0) */
/* USER CODE END */

#include "emac.h"
#include "sys_vim.h"

/* USER CODE BEGIN (1) */
extern volatile uint16 TestTx, TestRx;
/* USER CODE END */

/* Defining interface for all the emac instances */
hdkif_t hdkif_data[MAX_EMAC_INSTANCE];
/*SAFETYMCUSW 25 D MR:8.7 <APPROVED> "Statically allocated memory needs to be available to entire application." */
static uint8_t pbuf_array[MAX_RX_PBUF_ALLOC][MAX_TRANSFER_UNIT];
/*******************************************************************************
*                       INTERNAL MACRO DEFINITIONS
*******************************************************************************/
#define EMAC_CONTROL_RESET             (0x01U)
#define EMAC_SOFT_RESET                (0x01U)
#define EMAC_MAX_HEADER_DESC           (8U)
#define EMAC_UNICAST_DISABLE           (0xFFU)

/*******************************************************************************
*                        API FUNCTION DEFINITIONS
*******************************************************************************/
/**
* \brief   Enables the TXPULSE Interrupt Generation.
*
* \param   emacBase      Base address of the EMAC Module registers.
* \param   emacCtrlBase Base address of the EMAC CONTROL module registers
* \param   ctrlCore      Channel number for which the interrupt to be enabled in EMAC Control module
* \param   channel       Channel number for which interrupt to be enabled
*
* \return None
*
**/
/* SourceId : ETH_SourceId_001 */
/* DesignId : ETH_DesignId_001*/
/* Requirements : HL_ETH_SR15 */
void EMACTxIntPulseEnable(uint32 emacBase, uint32 emacCtrlBase, uint32 ctrlCore, uint32 channel)
{
    HWREG(emacBase + EMAC_TXINTMASKSET) |= ((uint32)1U << channel);

    HWREG(emacCtrlBase + EMAC_CTRL_CnTXEN(ctrlCore)) |= ((uint32)1U << channel);
}

/**
* \brief   Disables the TXPULSE Interrupt Generation.
*
* \param   emacBase      Base address of the EMAC Module registers.
* \param   emacCtrlBase Base address of the EMAC CONTROL module registers
* \param   ctrlCore      Channel number for which the interrupt to be enabled in EMAC Control module
* \param   channel       Channel number for which interrupt to be disabled
*
* \return None
*
**/
/* SourceId : ETH_SourceId_002 */
/* DesignId : ETH_DesignId_002*/
/* Requirements : HL_ETH_SR15 */
void EMACTxIntPulseDisable(uint32 emacBase, uint32 emacCtrlBase, uint32 ctrlCore, uint32 channel)
/*SAFETYMCUSW 1 J MR:14.1 <APPROVED> "LDRA Tool issue." */
{
    HWREG(emacBase + EMAC_TXINTMASKCLEAR) |= ((uint32)1U << channel);

    HWREG(emacCtrlBase + EMAC_CTRL_CnTXEN(ctrlCore)) &= (~((uint32)1U << channel));
}

/**
* \brief   Enables the RXPULSE Interrupt Generation.
*
* \param   emacBase      Base address of the EMAC Module registers.
* \param   emacCtrlBase Base address of the EMAC CONTROL module registers
* \param   ctrlCore      Control core for which the interrupt to be enabled.
* \param   channel       Channel number for which interrupt to be enabled
*
* \return None
*
**/
/* SourceId : ETH_SourceId_003 */
/* DesignId : ETH_DesignId_003*/
/* Requirements : HL_ETH_SR15 */
void EMACRxIntPulseEnable(uint32 emacBase, uint32 emacCtrlBase, uint32 ctrlCore, uint32 channel)
/*SAFETYMCUSW 1 J MR:14.1 <APPROVED> "LDRA Tool issue." */
{
    HWREG(emacBase + EMAC_RXINTMASKSET) |= ((uint32)1U << channel);

    HWREG(emacCtrlBase + EMAC_CTRL_CnRXEN(ctrlCore)) |= ((uint32)1U << channel);
}

/**
* \brief   Disables the RXPULSE Interrupt Generation.
*
* \param   emacBase      Base address of the EMAC Module registers.
* \param   emacCtrlBase Base address of the EMAC CONTROL module registers
* \param   ctrlCore      Control core for which the interrupt to be disabled.
* \param   channel       Channel number for which interrupt to be disabled
*
* \return None
*
**/
/* SourceId : ETH_SourceId_004 */
/* DesignId : ETH_DesignId_004*/
/* Requirements : HL_ETH_SR15 */
void EMACRxIntPulseDisable(uint32 emacBase, uint32 emacCtrlBase, uint32 ctrlCore, uint32 channel)
{
    HWREG(emacBase + EMAC_RXINTMASKCLEAR) |= ((uint32)1U << channel);

    HWREG(emacCtrlBase + EMAC_CTRL_CnRXEN(ctrlCore)) &= (~((uint32)1U << channel));
}
/**
* \brief   This API sets the RMII speed. The RMII Speed can be 10 Mbps or
*          100 Mbps
*
* \param   emacBase     Base address of the EMAC Module registers.
* \param   speed        speed for setting.
*          speed can take the following values. \n
*                EMAC_RMIISPEED_10MBPS - 10 Mbps \n
*                EMAC_RMIISPEED_100MBPS - 100 Mbps.
*
* \return None
*
**/
/* SourceId : ETH_SourceId_005 */
/* DesignId : ETH_DesignId_005*/
/* Requirements : HL_ETH_SR19 */
void EMACRMIISpeedSet(uint32 emacBase, uint32 speed)
{
    HWREG(emacBase + EMAC_MACCONTROL) &= (~(uint32)EMAC_MACCONTROL_RMIISPEED);

    HWREG(emacBase + EMAC_MACCONTROL) |= speed;
}
/* SourceId : ETH_SourceId_006 */
/* DesignId : ETH_DesignId_006*/
/* Requirements : HL_ETH_SR18 */
/**
* \brief   This API set the GMII bit, RX and TX are enabled for receive and transmit.
*          Note: This is not the API to enable MII.
* \param   emacBase     Base address of the EMAC Module registers.
*
* \return None
*
**/
void EMACMIIEnable(uint32 emacBase)
{
    HWREG(emacBase + EMAC_MACCONTROL) |= EMAC_MACCONTROL_GMIIEN;
}

/**
* \brief   This API clears the GMII bit, Rx and Tx are held in reset.
*          Note: This is not the API to disable MII.
* \param   emacBase     Base address of the EMAC Module registers.
*
* \return None
*
**/
/* SourceId : ETH_SourceId_007 */
/* DesignId : ETH_DesignId_007*/
/* Requirements : HL_ETH_SR18 */
void EMACMIIDisable(uint32 emacBase)
/*SAFETYMCUSW 1 J MR:14.1 <APPROVED> "LDRA Tool issue." */
{
    HWREG(emacBase + EMAC_MACCONTROL) &= (~(uint32)EMAC_MACCONTROL_GMIIEN);
}

/**
* \brief   This API sets the duplex mode of operation(full/half) for MAC.
*
* \param   emacBase     Base address of the EMAC Module registers.
* \param   duplexMode   duplex mode of operation.
*          duplexMode can take the following values. \n
*                EMAC_DUPLEX_FULL - Full Duplex \n
*                EMAC_DUPLEX_HALF - Half Duplex.
*
* \return None
*
**/
/* SourceId : ETH_SourceId_008 */
/* DesignId : ETH_DesignId_008*/
/* Requirements : HL_ETH_SR21 */
void EMACDuplexSet(uint32 emacBase, uint32 duplexMode)
{
    HWREG(emacBase + EMAC_MACCONTROL) &= (~(uint32)EMAC_MACCONTROL_FULLDUPLEX);

    HWREG(emacBase + EMAC_MACCONTROL) |= duplexMode;
}

/**
* \brief   API to enable the transmit in the TX Control Register
*          After the transmit is enabled, any write to TXHDP of
*          a channel will start transmission
*
* \param   emacBase      Base Address of the EMAC Module Registers.
*
* \return None
*
**/
/* SourceId : ETH_SourceId_009 */
/* DesignId : ETH_DesignId_009*/
/* Requirements : HL_ETH_SR21 */
void EMACTxEnable(uint32 emacBase)
{
    HWREG(emacBase + EMAC_TXCONTROL) = EMAC_TXCONTROL_TXEN;
}

/**
* \brief   API to disable the transmit in the TX Control Register
*
* \param   emacBase      Base Address of the EMAC Module Registers.
*
* \return None
*
**/
/* SourceId : ETH_SourceId_010 */
/* DesignId : ETH_DesignId_010*/
/* Requirements : HL_ETH_SR21 */
void EMACTxDisable(uint32 emacBase)
/*SAFETYMCUSW 1 J MR:14.1 <APPROVED> "LDRA Tool issue." */
{
    HWREG(emacBase + EMAC_TXCONTROL) = EMAC_TXCONTROL_TXDIS;
}

/**
* \brief   API to enable the receive in the RX Control Register
*          After the receive is enabled, and write to RXHDP of
*          a channel, the data can be received in the destination
*          specified by the corresponding RX buffer descriptor.
*
* \param   emacBase      Base Address of the EMAC Module Registers.
*
* \return None
*
**/
/* SourceId : ETH_SourceId_011*/
/* DesignId : ETH_DesignId_011*/
/* Requirements : HL_ETH_SR21 */
void EMACRxEnable(uint32 emacBase)
{
    HWREG(emacBase + EMAC_RXCONTROL) = EMAC_RXCONTROL_RXEN;
}

/**
* \brief   API to disable the receive in the RX Control Register
*
* \param   emacBase      Base Address of the EMAC Module Registers.
*
* \return None
*
**/
/* SourceId : ETH_SourceId_012*/
/* DesignId : ETH_DesignId_012*/
/* Requirements : HL_ETH_SR21 */
void EMACRxDisable(uint32 emacBase)
/*SAFETYMCUSW 1 J MR:14.1 <APPROVED> "LDRA Tool issue." */
{
    HWREG(emacBase + EMAC_RXCONTROL) = EMAC_RXCONTROL_RXDIS;
}

/**
* \brief   API to write the TX HDP register. If transmit is enabled,
*          write to the TX HDP will immediately start transmission.
*          The data will be taken from the buffer pointer of the TX buffer
*          descriptor written to the TX HDP
*
* \param   emacBase      Base Address of the EMAC Module Registers.\n
* \param   descHdr       Address of the TX buffer descriptor
* \param   channel       Channel Number
*
* \return None
*
**/
/* SourceId : ETH_SourceId_013*/
/* DesignId : ETH_DesignId_013*/
/* Requirements : HL_ETH_SR16 */
void EMACTxHdrDescPtrWrite(uint32 emacBase, uint32 descHdr,
                           uint32 channel)
{
    HWREG(emacBase + EMAC_TXHDP(channel)) = descHdr;
}

/**
* \brief   API to write the RX HDP register. If receive is enabled,
*          write to the RX HDP will enable data reception to point to
*          the corresponding RX buffer descriptor's buffer pointer.
*
* \param   emacBase      Base Address of the EMAC Module Registers.\n
* \param   descHdr       Address of the RX buffer descriptor
* \param   channel       Channel Number
*
* \return None
*
**/
/* SourceId : ETH_SourceId_014 */
/* DesignId : ETH_DesignId_014*/
/* Requirements : HL_ETH_SR16 */
void EMACRxHdrDescPtrWrite(uint32 emacBase, uint32 descHdr, uint32 channel)
{
    HWREG(emacBase + EMAC_RXHDP(channel)) = descHdr;
}

/**
* \brief   This API Initializes the EMAC and EMAC Control modules. The
*          EMAC Control module is reset, the CPPI RAM is cleared. also,
*          all the interrupts are disabled. This API does not enable any
*          interrupt or operation of the EMAC.
*
* \param   emacCtrlBase      Base Address of the EMAC Control module
*                            registers.\n
* \param   emacBase          Base address of the EMAC module registers
*
* \return None
*
**/
/* SourceId : ETH_SourceId_015 */
/* DesignId : ETH_DesignId_015*/
/* Requirements : HL_ETH_SR6 */
void EMACInit(uint32 emacCtrlBase, uint32 emacBase)
{
    uint32 cnt;

    /* Reset the EMAC Control Module. This clears the CPPI RAM also */
    HWREG(emacCtrlBase + EMAC_CTRL_SOFTRESET) = EMAC_CONTROL_RESET;

    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
    while((HWREG(emacCtrlBase + EMAC_CTRL_SOFTRESET) & EMAC_CONTROL_RESET) == EMAC_CONTROL_RESET)
    {
    } /* Wait */

    /* Reset the EMAC Module. This clears the CPPI RAM also */
    HWREG(emacBase + EMAC_SOFTRESET) = EMAC_SOFT_RESET;

    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
    while((HWREG(emacBase + EMAC_SOFTRESET) & EMAC_SOFT_RESET) == EMAC_SOFT_RESET )
    {
    } /* Wait */

    HWREG(emacBase + EMAC_MACCONTROL)= 0U;
    HWREG(emacBase + EMAC_RXCONTROL)= 0U;
    HWREG(emacBase + EMAC_TXCONTROL)= 0U;

    /* Initialize all the header descriptor pointer registers */
    for(cnt = 0U; cnt< EMAC_MAX_HEADER_DESC; cnt++)
    {
        HWREG(emacBase + EMAC_RXHDP(cnt)) = 0U;
        HWREG(emacBase + EMAC_TXHDP(cnt)) = 0U;
        HWREG(emacBase + EMAC_RXCP(cnt)) = 0U;
        HWREG(emacBase + EMAC_TXCP(cnt)) = 0U;
        HWREG(emacBase + EMAC_RXFREEBUFFER(cnt)) = 0xFFU;
    }
    /* Clear the interrupt enable for all the channels */
    HWREG(emacBase + EMAC_TXINTMASKCLEAR) = 0xFFU;
    HWREG(emacBase + EMAC_RXINTMASKCLEAR) = 0xFFU;

    HWREG(emacBase + EMAC_MACHASH1) = 0U;
    HWREG(emacBase + EMAC_MACHASH2) = 0U;

    HWREG(emacBase + EMAC_RXBUFFEROFFSET) = 0U;
}

/**
* \brief   Sets the MAC Address in MACSRCADDR registers.
*
* \param   emacBase      Base Address of the EMAC module registers.
* \param   macAddr       Start address of a MAC address array.
*                        The array[0] shall be the LSB of the MAC address
*
* \return None
*
**/
/* SourceId : ETH_SourceId_016 */
/* DesignId : ETH_DesignId_016*/
/* Requirements : HL_ETH_SR7 */
void EMACMACSrcAddrSet(uint32 emacBase, uint8 macAddr[6])
{
    HWREG(emacBase + EMAC_MACSRCADDRHI) = ((uint32)macAddr[5U] |((uint32)macAddr[4U] << 8U)
                                     |((uint32)macAddr[3U] << 16U) |((uint32)macAddr[2U] << 24U));
    HWREG(emacBase + EMAC_MACSRCADDRLO) = ((uint32)macAddr[1U] | ((uint32)macAddr[0U] << 8U));
}

/**
* \brief   Sets the MAC Address in MACADDR registers.
*
* \param   emacBase      Base Address of the EMAC module registers.
* \param   channel       Channel Number
* \param   matchFilt     Match or Filter
* \param   macAddr       Start address of a MAC address array.
*                        The array[0] shall be the LSB of the MAC address
*          matchFilt can take the following values \n
*          EMAC_MACADDR_NO_MATCH_NO_FILTER - Address is not used to match
*                                             or filter incoming packet. \n
*          EMAC_MACADDR_FILTER - Address is used to filter incoming packets \n
*          EMAC_MACADDR_MATCH - Address is used to match incoming packets \n
*
* \return None
*
**/
/* SourceId : ETH_SourceId_017 */
/* DesignId : ETH_DesignId_017*/
/* Requirements : HL_ETH_SR7 */
void EMACMACAddrSet(uint32 emacBase, uint32 channel, uint8 macAddr[6], uint32 matchFilt)
{
    HWREG(emacBase + EMAC_MACINDEX) = channel;

    HWREG(emacBase + EMAC_MACADDRHI) = ((uint32)macAddr[5U] |((uint32)macAddr[4U] << 8U)
                                     |((uint32)macAddr[3U] << 16U) |((uint32)macAddr[2U] << 24U));
    HWREG(emacBase + EMAC_MACADDRLO) = ((uint32)macAddr[1U] | ((uint32)macAddr[0U] << 8U)
                                     | matchFilt | (channel << 16U));
}

/**
* \brief   Acknowledges an interrupt processed to the EMAC Control Core.
*
* \param   emacBase      Base Address of the EMAC module registers.
* \param   eoiFlag       Type of interrupt to acknowledge to the EMAC Control
*                         module.
*          eoiFlag can take the following values \n
*             EMAC_INT_CORE0_TX - Core 0 TX Interrupt
*             EMAC_INT_CORE1_TX - Core 1 TX Interrupt
*             EMAC_INT_CORE2_TX - Core 2 TX Interrupt
*             EMAC_INT_CORE0_RX - Core 0 RX Interrupt
*             EMAC_INT_CORE1_RX - Core 1 RX Interrupt
*             EMAC_INT_CORE2_RX - Core 2 RX Interrupt
* \return None
*
**/
/* SourceId : ETH_SourceId_018 */
/* DesignId : ETH_DesignId_018*/
/* Requirements : HL_ETH_SR15 */
void EMACCoreIntAck(uint32 emacBase, uint32 eoiFlag)
{
    /* Acknowledge the EMAC Control Core */
    HWREG(emacBase + EMAC_MACEOIVECTOR) = eoiFlag;
}

/**
* \brief   Writes the the TX Completion Pointer for a specific channel
*
* \param   emacBase      Base Address of the EMAC module registers.
* \param   channel       Channel Number.
* \param   comPtr        Completion Pointer Value to be written
*
* \return None
*
**/
/* SourceId : ETH_SourceId_019 */
/* DesignId : ETH_DesignId_019*/
/* Requirements : HL_ETH_SR27 */
void EMACTxCPWrite(uint32 emacBase, uint32 channel, uint32 comPtr)
{
    HWREG(emacBase + EMAC_TXCP(channel)) = comPtr;
}

/**
* \brief   Writes the the RX Completion Pointer for a specific channel
*
* \param   emacBase      Base Address of the EMAC module registers.
* \param   channel       Channel Number.
* \param   comPtr        Completion Pointer Value to be written
*
* \return None
*
**/
/* SourceId : ETH_SourceId_020 */
/* DesignId : ETH_DesignId_020*/
/* Requirements : HL_ETH_SR27 */
void EMACRxCPWrite(uint32 emacBase, uint32 channel, uint32 comPtr)
{
    HWREG(emacBase + EMAC_RXCP(channel)) = comPtr;
}

/**
* \brief   Enables a specific channel to receive broadcast frames
*
* \param   emacBase      Base Address of the EMAC module registers.
* \param   channel       Channel Number.
*
* \return None
*
**/
/* SourceId : ETH_SourceId_021 */
/* DesignId : ETH_DesignId_021*/
/* Requirements : HL_ETH_SR28 */
void EMACRxBroadCastEnable(uint32 emacBase, uint32 channel)
{
    HWREG(emacBase + EMAC_RXMBPENABLE) &= (~(uint32)EMAC_RXMBPENABLE_RXBROADCH);

    HWREG(emacBase + EMAC_RXMBPENABLE) |= ((uint32)EMAC_RXMBPENABLE_RXBROADEN | ((uint32)channel << (uint32)EMAC_RXMBPENABLE_RXBROADCH_SHIFT));
}

/**
* \brief   Disables a specific channel to receive broadcast frames
*
* \param   emacBase      Base Address of the EMAC module registers.
* \param   channel       Channel Number.
*
* \return None
*
**/
/* SourceId : ETH_SourceId_022 */
/* DesignId : ETH_DesignId_022*/
/* Requirements : HL_ETH_SR28 */
void EMACRxBroadCastDisable(uint32 emacBase, uint32 channel)
/*SAFETYMCUSW 1 J MR:14.1 <APPROVED> "LDRA Tool issue." */
{
    HWREG(emacBase + EMAC_RXMBPENABLE) &= (~(uint32)EMAC_RXMBPENABLE_RXBROADCH);
    /* Broadcast Frames are filtered. */
    HWREG(emacBase + EMAC_RXMBPENABLE) &= (~(uint32)EMAC_RXMBPENABLE_RXBROADEN);
}

/**
* \brief   Enables a specific channel to receive multicast frames
*
* \param   emacBase      Base Address of the EMAC module registers.
* \param   channel       Channel Number.
*
* \return None
*
**/
/* SourceId : ETH_SourceId_023 */
/* DesignId : ETH_DesignId_023*/
/* Requirements : HL_ETH_SR28 */
void EMACRxMultiCastEnable(uint32 emacBase, uint32 channel)
{
    HWREG(emacBase + EMAC_RXMBPENABLE) &= (~(uint32)EMAC_RXMBPENABLE_RXMULTCH);

    HWREG(emacBase + EMAC_RXMBPENABLE) |= ((uint32)EMAC_RXMBPENABLE_RXMULTEN |(channel));
}

/**
* \brief   Disables a specific channel to receive multicast frames
*
* \param   emacBase      Base Address of the EMAC module registers.
* \param   channel       Channel Number.
*
* \return None
*
**/
/* SourceId : ETH_SourceId_024 */
/* DesignId : ETH_DesignId_024*/
/* Requirements : HL_ETH_SR28 */
void EMACRxMultiCastDisable(uint32 emacBase, uint32 channel)
{
    HWREG(emacBase + EMAC_RXMBPENABLE) &= (~(uint32)EMAC_RXMBPENABLE_RXMULTCH);

    HWREG(emacBase + EMAC_RXMBPENABLE) &= (~(uint32)EMAC_RXMBPENABLE_RXMULTEN);
}

/**
* \brief   Enables unicast for a specific channel
*
* \param   emacBase      Base Address of the EMAC module registers.
* \param   channel       Channel Number.
*
* \return None
*
**/
/* SourceId : ETH_SourceId_025 */
/* DesignId : ETH_DesignId_025*/
/* Requirements : HL_ETH_SR14 */
void EMACRxUnicastSet(uint32 emacBase, uint32 channel)
{
    HWREG(emacBase + EMAC_RXUNICASTSET) |= ((uint32)1U << channel);
}

/**
* \brief   Disables unicast for a specific channel
*
* \param   emacBase      Base Address of the EMAC module registers.
* \param   channel       Channel Number.
*
* \return None
*
**/
/* SourceId : ETH_SourceId_026 */
/* DesignId : ETH_DesignId_026*/
/* Requirements : HL_ETH_SR14 */
void EMACRxUnicastClear(uint32 emacBase, uint32 channel)
/*SAFETYMCUSW 1 J MR:14.1 <APPROVED> "LDRA Tool issue." */
{
    HWREG(emacBase + EMAC_RXUNICASTCLEAR) |= ((uint32)1U << channel);
}

/**
* \brief   Set the free buffers for a specific channel
*
* \param   emacBase      Base Address of the EMAC module registers.
* \param   channel       Channel Number.
* \param   nBuf          Number of free buffers
*
* \return None
*
**/
/* SourceId : ETH_SourceId_027 */
/* DesignId : ETH_DesignId_027*/
/* Requirements : HL_ETH_SR20 */
void EMACNumFreeBufSet(uint32 emacBase, uint32 channel,
                       uint32 nBuf)
{
    HWREG(emacBase + EMAC_RXFREEBUFFER(channel)) = nBuf;
}

/**
* \brief   Gets the interrupt vectors of EMAC, which are pending
*
* \param   emacBase      Base Address of the EMAC module registers.
*
* \return Vectors
*
**/
/* SourceId : ETH_SourceId_028 */
/* DesignId : ETH_DesignId_028*/
/* Requirements : HL_ETH_SR15 */
uint32 EMACIntVectorGet(uint32 emacBase)
{
    return (HWREG(emacBase + EMAC_MACINVECTOR));
}

/**
* Function to setup the instance parameters inside the interface
* @param   hdkif Network interface structure
* @return none.
*/
/* SourceId : ETH_SourceId_029 */
/* DesignId : ETH_DesignId_029*/
/* Requirements : HL_ETH_SR6 */
void EMACInstConfig(hdkif_t *hdkif)
{
    hdkif->emac_base = EMAC_0_BASE;
    hdkif->emac_ctrl_base = EMAC_CTRL_0_BASE;
    hdkif->emac_ctrl_ram = EMAC_CTRL_RAM_0_BASE;
    hdkif->mdio_base = MDIO_BASE;
    hdkif->phy_addr = 1U;
    /* (MISRA-C:2004 10.1/R) MISRA error reported with Code Composer Studio MISRA checker. */
    hdkif->phy_autoneg = &Dp83640AutoNegotiate;
    hdkif->phy_partnerability = &Dp83640PartnerAbilityGet;
}

/**
* Function to setup the link. AutoNegotiates with the phy for link
* setup and set the EMAC with the result of autonegotiation.
* @param hdkif Network interface structure.
* @return ERR_OK if everything passed
*         others if not passed
*/
/* SourceId : ETH_SourceId_030 */
/* DesignId : ETH_DesignId_030*/
/* Requirements : HL_ETH_SR6 */
uint32 EMACLinkSetup(hdkif_t *hdkif) {
uint32 linkstat = EMAC_ERR_CONNECT;
uint16 partnr_ablty = 0U;
uint32 phyduplex = EMAC_DUPLEX_HALF;
volatile uint32 delay = 0xFFFFFU;

    if(Dp83640AutoNegotiate((uint32)hdkif->mdio_base, (uint32)hdkif->phy_addr,
                             (uint16)((uint16)DP83640_100BTX | (uint16)DP83640_100BTX_FD
                              | (uint16)DP83640_10BT | (uint16)DP83640_10BT_FD)) == TRUE) {
      linkstat = EMAC_ERR_OK;
      /* (MISRA-C:2004 10.1/R) MISRA error reported with Code Composer Studio MISRA checker (due to use of & ?) */
      (void)Dp83640PartnerAbilityGet(hdkif->mdio_base, hdkif->phy_addr,
                                &partnr_ablty);

      /* Check for 100 Mbps and duplex capability */
      if((partnr_ablty & DP83640_100BTX_FD) != 0U) {
        phyduplex = EMAC_DUPLEX_FULL;
      }
    }

else {
    linkstat = EMAC_ERR_CONNECT;
}

/* Set the EMAC with the negotiation results if it is successful */
if(linkstat == EMAC_ERR_OK) {
    EMACDuplexSet(hdkif->emac_base, phyduplex);
}

/* Wait for the MII to settle down */
/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
while(delay != 0U)
{
    delay--;
}

return linkstat;
}

/**
* \brief   Perform a transmit queue teardown, that is, transmission is aborted.
*
* \param   emacBase      Base Address of the EMAC module registers.
* \param   channel       Channel Number.
*
* \return None
*
**/
/* SourceId : ETH_SourceId_031 */
/* DesignId : ETH_DesignId_031*/
/* Requirements : HL_ETH_SR22 */
void EMACTxTeardown(uint32 emacBase, uint32 channel)
{
    HWREG(emacBase + EMAC_TXTEARDOWN) &= (channel);
}

/**
* \brief   Perform a receive queue teardown, that is, reception is aborted.
*
* \param   emacBase      Base Address of the EMAC module registers.
* \param   channel       Channel Number.
*
* \return None
*
**/
/* SourceId : ETH_SourceId_032 */
/* DesignId : ETH_DesignId_032*/
/* Requirements : HL_ETH_SR22 */
void EMACRxTeardown(uint32 emacBase, uint32 channel)
{
    HWREG(emacBase + EMAC_RXTEARDOWN) &= (channel);
}

/**
* \brief   Perform multicast frame filtering using the MAC Hash Registers.
*
* \param   emacBase      Base Address of the EMAC module registers.
* \param   hashTable     The hash table which specifies which bits are to be accepted.
*
* \return None
*
**/
/* SourceId : ETH_SourceId_033 */
/* DesignId : ETH_DesignId_033*/
/* Requirements : HL_ETH_SR24 */
void EMACFrameSelect(uint32 emacBase, uint64 hashTable)
{
    HWREG(emacBase + EMAC_MACHASH1) = (uint32)(hashTable & 0xFFFFFFFFU);
    HWREG(emacBase + EMAC_MACHASH2) = (uint32)(hashTable >> 32U);
}

/**
* \brief   Sets the Transmit Queue Priority type in the MACCONTROL Register
*
* \param   emacBase      Base Address of the EMAC module registers.
* \param   txPType       The Transmit Queue Priority Type.
*                        0 results in a round-robin scheme being used to select the next channel, while 1 results
*                        in a fixed-priority scheme( channel 7 highest priority).
*
* \return None
*
**/
/* SourceId : ETH_SourceId_034 */
/* DesignId : ETH_DesignId_034*/
/* Requirements : HL_ETH_SR25 */
void EMACTxPrioritySelect(uint32 emacBase, uint32 txPType)
{

    /* 1- The queue uses a fixed-priority (channel 7 highest priority) scheme */
    if(txPType == 1U)
    {
        HWREG(emacBase + EMAC_MACCONTROL) &= (~(uint32)(EMAC_MACCONTROL_TXPTYPE));
        HWREG(emacBase + EMAC_MACCONTROL) |= EMAC_MACCONTROL_TXPTYPE;
    }
    else
    {
        HWREG(emacBase + EMAC_MACCONTROL) &= (~(uint32)(EMAC_MACCONTROL_TXPTYPE));
    }
}

/**
* \brief   Performs a soft reset of the EMAC and EMAC Control Modules.
*
* \param   emacCtrlBase Base address of the EMAC CONTROL module registers
* \param   emacBase      Base Address of the EMAC module registers.
* \return None
*
**/
/* SourceId : ETH_SourceId_035 */
/* DesignId : ETH_DesignId_035*/
/* Requirements : HL_ETH_SR26 */
void EMACSoftReset(uint32 emacCtrlBase, uint32 emacBase)
{
    /* Reset the EMAC Control Module. This clears the CPPI RAM also */
    HWREG(emacCtrlBase + EMAC_CTRL_SOFTRESET) = EMAC_CONTROL_RESET;

    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
    while((HWREG(emacCtrlBase + EMAC_CTRL_SOFTRESET) & EMAC_CONTROL_RESET) == EMAC_CONTROL_RESET)
    {
        /* Wait for the reset to complete */
    }

    /* Reset the EMAC Module. */
    HWREG(emacBase + EMAC_SOFTRESET) = EMAC_SOFT_RESET;

    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
    while((HWREG(emacBase + EMAC_SOFTRESET) & EMAC_SOFT_RESET) == EMAC_SOFT_RESET )
    {
        /* Wait for the Reset to complete */
    }

}

/**
* \brief   Enable Idle State of the EMAC Module.
*
* \param   emacBase      Base Address of the EMAC module registers.
* \return None
*
**/
/* SourceId : ETH_SourceId_036 */
/* DesignId : ETH_DesignId_036*/
/* Requirements : HL_ETH_SR32 */
void EMACEnableIdleState(uint32 emacBase)
{
        HWREG(emacBase + EMAC_MACCONTROL) |= EMAC_MACCONTROL_CMDIDLE;
}

/**
* \brief   Disable Idle State of the EMAC Module.
*
* \param   emacBase      Base Address of the EMAC module registers.
* \return None
*
**/
/* SourceId : ETH_SourceId_037 */
/* DesignId : ETH_DesignId_037*/
/* Requirements : HL_ETH_SR32 */
void EMACDisableIdleState(uint32 emacBase)
{
        HWREG(emacBase + EMAC_MACCONTROL) &= (~(uint32)(EMAC_MACCONTROL_CMDIDLE));
}

/**
* \brief   Enables Loopback Mode.
*
* \param   emacBase      Base Address of the EMAC module registers.
* \return None
*
**/
/* SourceId : ETH_SourceId_038 */
/* DesignId : ETH_DesignId_038*/
/* Requirements : HL_ETH_SR50 */
void EMACEnableLoopback(uint32 emacBase)
/*SAFETYMCUSW 1 J MR:14.1 <APPROVED> "LDRA Tool issue." */
{
    uint32 GMIIENval=0U;
    /*Store the value of GMIIEN bit before deasserting it */
    GMIIENval = HWREG(emacBase + EMAC_MACCONTROL) & EMAC_MACCONTROL_GMIIEN;
    HWREG(emacBase + EMAC_MACCONTROL) &= (~(uint32)EMAC_MACCONTROL_GMIIEN);

    /*Enable Loopback */
    HWREG(emacBase + EMAC_MACCONTROL) |= EMAC_MACCONTROL_LOOPBACK;

    /*Restore the value of GMIIEN bit */
    HWREG(emacBase + EMAC_MACCONTROL) |= GMIIENval;
}

/**
* \brief   Disables Loopback Mode.
*
* \param   emacBase      Base Address of the EMAC module registers.
* \return None
*
**/
/* SourceId : ETH_SourceId_039 */
/* DesignId : ETH_DesignId_039*/
/* Requirements : HL_ETH_SR50 */
void EMACDisableLoopback(uint32 emacBase)
{
    uint32 GMIIENval=0U;

    /*Store the value of GMIIEN bit before deasserting it */
    GMIIENval = HWREG(emacBase + EMAC_MACCONTROL) & EMAC_MACCONTROL_GMIIEN;
    HWREG(emacBase + EMAC_MACCONTROL) &= (~(uint32)EMAC_MACCONTROL_GMIIEN);

    /*Disable Loopback */
    HWREG(emacBase + EMAC_MACCONTROL) &= (~(uint32)EMAC_MACCONTROL_LOOPBACK);

    /*Restore the value of GMIIEN bit */
    HWREG(emacBase + EMAC_MACCONTROL) |= GMIIENval;
}

/**
* \brief   Enable Transmit Flow Control.
*
* \param   emacBase      Base Address of the EMAC module registers.
* \return None
*
**/
/* SourceId : ETH_SourceId_040 */
/* DesignId : ETH_DesignId_040*/
/* Requirements : HL_ETH_SR20 */
void EMACTxFlowControlEnable(uint32 emacBase)
{
    HWREG(emacBase + EMAC_MACCONTROL) |= EMAC_MACCONTROL_TXFLOWEN;
}

/**
* \brief   Disable Transmit Flow Control.
*
* \param   emacBase      Base Address of the EMAC module registers.
* \return None
*
**/
/* SourceId : ETH_SourceId_041 */
/* DesignId : ETH_DesignId_041*/
/* Requirements : HL_ETH_SR20 */
void EMACTxFlowControlDisable(uint32 emacBase)
{
    HWREG(emacBase + EMAC_MACCONTROL) &= (~(uint32)EMAC_MACCONTROL_TXFLOWEN);
}

/**
* \brief   Enable Receive Flow Control.
*
* \param   emacBase      Base Address of the EMAC module registers.
* \return None
*
**/
/* SourceId : ETH_SourceId_042 */
/* DesignId : ETH_DesignId_042*/
/* Requirements : HL_ETH_SR20 */
void EMACRxFlowControlEnable(uint32 emacBase)
{
    HWREG(emacBase + EMAC_MACCONTROL) |= EMAC_MACCONTROL_RXBUFFERFLOWEN;
}

/**
* \brief   Disable Receive Flow Control.
*
* \param   emacBase      Base Address of the EMAC module registers.
* \return None
*
**/
/* SourceId : ETH_SourceId_043 */
/* DesignId : ETH_DesignId_043*/
/* Requirements : HL_ETH_SR20 */
void EMACRxFlowControlDisable(uint32 emacBase)
{
    HWREG(emacBase + EMAC_MACCONTROL) &= (~(uint32)EMAC_MACCONTROL_RXBUFFERFLOWEN);
}

/**
* \brief   Receive flow threshold. These bits contain the threshold value for issuing flow control on incoming frames for channel n (when enabled).
*
* \param   emacBase      Base Address of the EMAC module registers.
* \param   channel       Channel Number
* \param   threshold     threshold value for issuing flow control on incoming frames for the given channel
* \return None
*
**/
/* SourceId : ETH_SourceId_044 */
/* DesignId : ETH_DesignId_044*/
/* Requirements : HL_ETH_SR20 */
void EMACRxSetFlowThreshold(uint32 emacBase, uint32 channel, uint32 threshold)
{
    HWREG(emacBase + EMAC_RXFLOWTHRESH(channel)) &= (0x0U);
    HWREG(emacBase + EMAC_RXFLOWTHRESH(channel)) |= threshold;
}

/**
* \brief               This function reads the contents of the 36 network statistics registers that are present in the module.
* \param   emacBase    Base Address of the EMAC module registers.
* \param   statRegNo   The number of the register with RXGOODFRAMES (Offset= 0x200) being 0. Refer the Technical Reference Manual for the list of registers and their contents.
* \return uint32
**/
/* SourceId : ETH_SourceId_045 */
/* DesignId : ETH_DesignId_045*/
/* Requirements : HL_ETH_SR29 */
uint32 EMACReadNetStatRegisters(uint32 emacBase, uint32 statRegNo)
{
    return HWREG(emacBase + EMAC_NETSTATREGS(statRegNo));
}

/**
* \brief   Function to read values of Transmit Interrupt Status registers (TXINTSTATMASKED and TXINTSTATRAW)
*
* \param   emacBase      Base Address of the EMAC module registers.
* \param   channel       Channel Number
* \param   txintstat     pointer to the emac_tx_int_status Structure that will store the register values that have been read
* \return None
*
**/
/* SourceId : ETH_SourceId_046 */
/* DesignId : ETH_DesignId_046*/
/* Requirements : HL_ETH_SR23 */
void EMACTxIntStat(uint32 emacBase, uint32 channel, emac_tx_int_status_t *txintstat)
{
    txintstat->intstatmasked = (HWREG(emacBase + EMAC_TXINTSTATMASKED) & ((uint32)1U << channel));
    txintstat->intstatraw = (HWREG(emacBase + EMAC_TXINTSTATRAW) & ((uint32)1U << channel));
}

/**
* \brief   Function to read values of Receive Interrupt Status registers (RXINTSTATMASKED, RXINTSTATRAW)
*
* \param   emacBase      Base Address of the EMAC module registers.
* \param   channel       Channel Number
* \param rxintstat      pointer to the emac_rx_int_status Structure that will store the register values that have been read.
* \return None
**/
/* SourceId : ETH_SourceId_047 */
/* DesignId : ETH_DesignId_047*/
/* Requirements : HL_ETH_SR23 */
void EMACRxIntStat(uint32 emacBase, uint32 channel, emac_rx_int_status_t *rxintstat)
{
    rxintstat->intstatmasked_pend = (HWREG(emacBase + EMAC_RXINTSTATMASKED) & ((uint32)0x1U << (uint32)(channel)));
    rxintstat->intstatmasked_threshpend = (HWREG(emacBase + EMAC_RXINTSTATMASKED) & ((uint32)0x1U << ((uint32)0x8U + (uint32)(channel))));

    rxintstat->intstatraw_pend = (HWREG(emacBase + EMAC_RXINTSTATRAW) & ((uint32)0x1U << (uint32)(channel)));
    rxintstat->intstatraw_threshpend = (HWREG(emacBase + EMAC_RXINTSTATRAW) & ((uint32)0x1U << ((uint32)0x8U + (uint32)(channel))));
}

/**
* \brief   Tx and Rx Buffer Descriptors are initialized. Buffer pointers are allocated to the Rx Descriptors.
*
* \param   hdkif   network interface structure
* \return None
*
**/
/* SourceId : ETH_SourceId_048 */
/* DesignId : ETH_DesignId_048*/
/* Requirements : HL_ETH_SR17,HL_ETH_SR30 */
void EMACDMAInit(hdkif_t *hdkif)
{

      uint32 num_bd, pbuf_cnt = 0U;
      volatile emac_tx_bd_t *curr_txbd, *last_txbd;
      volatile emac_rx_bd_t *curr_bd, *last_bd;
      txch_t *txch_dma;
      rxch_t *rxch_dma;
      uint8_t *p;

      txch_dma = &(hdkif->txchptr);

      /**
      * Initialize the Descriptor Memory For TX and RX
      * Only single channel is supported for both TX and RX
      */
      /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
      /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
      txch_dma->free_head = (volatile emac_tx_bd_t*)(hdkif->emac_ctrl_ram);
      txch_dma->next_bd_to_process = txch_dma->free_head;
      txch_dma->active_tail = NULL;

      /* Set the number of descriptors for the channel */
      num_bd = (SIZE_EMAC_CTRL_RAM >> 1U) / sizeof(emac_tx_bd_t);

      /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
      curr_txbd = txch_dma->free_head;
      /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
      last_txbd = curr_txbd;

      /* Initialize all the TX buffer Descriptors */
      while(num_bd != 0U) {
        /*SAFETYMCUSW 567 S MR:17.1,17.4 <APPROVED> "Struct pointer used for linked list is incremented." */
        curr_txbd->next = curr_txbd + 1U;
        /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
        curr_txbd->flags_pktlen = 0U;
        /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
        last_txbd = curr_txbd;
        /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
        curr_txbd = curr_txbd->next;
        num_bd--;
      }
      /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
      /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
      last_txbd->next = txch_dma->free_head;

      /* Initialize the descriptors for the RX channel */
      /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
      rxch_dma = &(hdkif->rxchptr);
      /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
      /*SAFETYMCUSW 567 S MR:17.1,17.4 <APPROVED> "Struct pointer used for linked list is incremented." */
      curr_txbd++;
      /*SAFETYMCUSW 94 S MR:11.1,11.2,11.4 <APPROVED> "Linked List pointer needs to be assigned." */
      /*SAFETYMCUSW 95 S MR:11.1,11.4 <APPROVED> "Linked List pointer needs to be assigned." */
      /*SAFETYMCUSW 344 S MR:11.5 <APPROVED> "Linked List pointer needs to be assigned to a different structure." */
      /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
      rxch_dma->active_head = (volatile emac_rx_bd_t *)curr_txbd;

      /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
      rxch_dma->free_head = NULL;
      /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
      curr_bd = rxch_dma->active_head;
      /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
      last_bd = curr_bd;

      /*
      ** Static allocation of a specific number of packet buffers as specified by MAX_RX_PBUF_ALLOC, whose value is entered by the user in HALCoGen GUI.
      */

      /*Commented part of allocation of pbufs need to check whether its true*/

      for(pbuf_cnt = 0U;pbuf_cnt < MAX_RX_PBUF_ALLOC;pbuf_cnt++)
        {
         /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
         p = pbuf_array[pbuf_cnt];
         /*SAFETYMCUSW 439 S MR:11.3 <APPROVED> "RHS is a pointer value required to be stored. - Advisory as per MISRA" */
         /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
         curr_bd->bufptr = (uint32)p;
         /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
         curr_bd->bufoff_len = MAX_TRANSFER_UNIT;
         /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
         curr_bd->flags_pktlen = EMAC_BUF_DESC_OWNER;
         if (pbuf_cnt == (MAX_RX_PBUF_ALLOC - 1U))
         {
             /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
             curr_bd->next = NULL;
             /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
             last_bd = curr_bd;

         }
         else
         {
             /*SAFETYMCUSW 567 S MR:17.1,17.4 <APPROVED> "Struct pointer used for linked list is incremented." */
             curr_bd->next = (curr_bd + 1U);
             /*SAFETYMCUSW 567 S MR:17.1,17.4 <APPROVED> "Struct pointer used for linked list is incremented." */
             curr_bd++;
             /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
             last_bd = curr_bd;
         }
       }

      /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
      /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
      last_bd->next = NULL;
      /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
      rxch_dma->active_tail = last_bd;
}

/**
* \brief   Initializes the EMAC module for transmission and reception.
*
* \param   macaddr    MAC Address of the Module.
* \param   channel       Channel Number.
*
* \return EMAC_ERR_OK if everything gets initialized
*          EMAC_ERR_CONN in case of an error in connecting.
*
**/
/* SourceId : ETH_SourceId_049 */
/* DesignId : ETH_DesignId_049*/
/* Requirements : HL_ETH_SR6 */
uint32 EMACHWInit(uint8_t macaddr[6U])
{
uint32 temp, channel;
volatile uint32 phyID=0U;
volatile uint32 delay = 0xFFFU;
uint32 phyIdReadCount = 0xFFFFU;
volatile uint32 phyLinkRetries = 0xFFFFU;
hdkif_t *hdkif;
rxch_t *rxch;
uint32 retVal = EMAC_ERR_OK;
uint32 emacBase = 0U;
#if(EMAC_MII_ENABLE == 0U)
uint16 partnr_spd;
#endif

hdkif = &hdkif_data[0U];
EMACInstConfig(hdkif);
/* set MAC hardware address */
for(temp = 0U; temp < EMAC_HWADDR_LEN; temp++) {
    hdkif->mac_addr[temp] = macaddr[(EMAC_HWADDR_LEN - 1U) - temp];
}
/*Initialize the EMAC, EMAC Control and MDIO modules. */
EMACInit(hdkif->emac_ctrl_base, hdkif->emac_base);
MDIOInit(hdkif->mdio_base, MDIO_FREQ_INPUT, MDIO_FREQ_OUTPUT);

/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
while(delay != 0U)
{
/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
    delay--;
}

/* Set the MAC Addresses in EMAC hardware */
emacBase = hdkif->emac_base; /* MISRA Code Fix (12.2) */
EMACMACSrcAddrSet(emacBase, hdkif->mac_addr);
for(channel = 0U; channel < 8U; channel++) {
       emacBase = hdkif->emac_base;
       EMACMACAddrSet(emacBase, (uint32)EMAC_CHANNELNUMBER, hdkif->mac_addr, EMAC_MACADDR_MATCH);
}

/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
while ((phyID == 0U) && (phyIdReadCount > 0U)) {
      phyID = Dp83640IDGet(hdkif->mdio_base,hdkif->phy_addr);
      phyIdReadCount--;
}

if (0U == phyID) {
      retVal = EMAC_ERR_CONNECT;
} else {

}

if((uint32)0U == ((MDIOPhyAliveStatusGet(hdkif->mdio_base)
        >> hdkif->phy_addr) & (uint32)0x01U )) {
    retVal = EMAC_ERR_CONNECT;
} else {

}

#if(EMAC_MII_ENABLE == 0U)

   Dp83640PartnerSpdGet(hdkif->mdio_base, hdkif->phy_addr, &partnr_spd);
   if((partnr_spd & 2U)==0U)
   {
       EMACRMIISpeedSet(hdkif->emac_base, EMAC_MACCONTROL_RMIISPEED);
   }
#endif

if(!Dp83640LinkStatusGet(hdkif->mdio_base, (uint32)EMAC_PHYADDRESS, (uint32)phyLinkRetries)) {
      retVal = EMAC_ERR_CONNECT;
} else {

}

if(EMACLinkSetup(hdkif) != EMAC_ERR_OK) {
    retVal = EMAC_ERR_CONNECT;
} else {

}

/* The transmit and receive buffer descriptors are initialized here.
   * Also, packet buffers are allocated to the receive buffer descriptors.
   */

EMACDMAInit(hdkif);

/* Acknowledge receive and transmit interrupts for proper interrupt pulsing*/
EMACCoreIntAck(hdkif->emac_base, (uint32)EMAC_INT_CORE0_RX);
EMACCoreIntAck(hdkif->emac_base, (uint32)EMAC_INT_CORE0_TX);

/* Enable GMII bit in the MACCONTROL Rgister*/
/*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Parameter is taken as input from GUI." */
EMACMIIEnable(hdkif->emac_base);

/* Enable Broadcast if enabled in the GUI. */
/*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Parameter is taken as input from GUI." */
#if(EMAC_BROADCAST_ENABLE)
      EMACRxBroadCastEnable(hdkif->emac_base, (uint32)EMAC_CHANNELNUMBER);
#else
   /*SAFETYMCUSW 1 J MR:14.1 <APPROVED> "If condition parameter is taken as input from GUI." */
   /*SAFETYMCUSW 1 J MR:14.1 <APPROVED> "If condition parameter is taken as input from GUI." */
      EMACRxBroadCastDisable(hdkif->emac_base, (uint32)EMAC_CHANNELNUMBER);
#endif

/* Enable Broadcast if enabled in the GUI. */
/*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Parameter is taken as input from GUI." */
#if(EMAC_UNICAST_ENABLE)
      EMACRxUnicastSet(hdkif->emac_base, (uint32)EMAC_CHANNELNUMBER);
#else
      /*SAFETYMCUSW 1 J MR:14.1 <APPROVED> "If condition parameter is taken as input from GUI." */
      EMACRxUnicastClear(hdkif->emac_base, (uint32)EMAC_CHANNELNUMBER);
#endif

/*Enable Full Duplex or Half-Duplex mode based on GUI Input. */
/*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Parameter is taken as input from GUI." */
#if (EMAC_FULL_DUPLEX_ENABLE)
        EMACDuplexSet(EMAC_0_BASE, (uint32)EMAC_DUPLEX_FULL);
#else
        /*SAFETYMCUSW 1 J MR:14.1 <APPROVED> "If condition arameter is taken as input from GUI." */
        EMACDuplexSet(EMAC_0_BASE, (uint32)EMAC_DUPLEX_HALF);
#endif

/* Enable Loopback based on GUI Input */
/*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Parameter is taken as input from GUI." */
#if(EMAC_LOOPBACK_ENABLE)
      EMACEnableLoopback(hdkif->emac_base);
#else
      /*SAFETYMCUSW 1 J MR:14.1 <APPROVED> "If condition parameter is taken as input from GUI." */
      EMACDisableLoopback(hdkif->emac_base);
#endif

/* Enable Transmit and Transmit Interrupt */
/*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Parameter is taken as input from GUI." */
#if(EMAC_TX_ENABLE)
      EMACTxEnable(hdkif->emac_base);
      EMACTxIntPulseEnable(hdkif->emac_base, hdkif->emac_ctrl_base, 0x00, (uint32)EMAC_CHANNELNUMBER);
#else
      /*SAFETYMCUSW 1 J MR:14.1 <APPROVED> "If condition parameter is taken as input from GUI." */
      /*SAFETYMCUSW 1 J MR:14.1 <APPROVED> "If condition parameter is taken as input from GUI." */
      EMACTxDisable(hdkif->emac_base);
      EMACTxIntPulseDisable(hdkif->emac_base, hdkif->emac_ctrl_base, 0x00, (uint32)EMAC_CHANNELNUMBER);
#endif

/* Enable Receive and Receive Interrupt. Then start receiving by writing to the HDP register. */
/*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Parameter is taken as input from GUI." */
#if(EMAC_RX_ENABLE)
      EMACNumFreeBufSet(hdkif->emac_base,(uint32)EMAC_CHANNELNUMBER , (uint32)MAX_RX_PBUF_ALLOC);
      EMACRxEnable(hdkif->emac_base);
      EMACRxIntPulseEnable(hdkif->emac_base, hdkif->emac_ctrl_base, 0x00, (uint32)EMAC_CHANNELNUMBER);
      rxch = &(hdkif->rxchptr);
      /* Write to the RX HDP for channel 0 */
      /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
      EMACRxHdrDescPtrWrite(hdkif->emac_base, (uint32)rxch->active_head, (uint32)EMAC_CHANNELNUMBER);
#else
      /*SAFETYMCUSW 1 J MR:14.1 <APPROVED> "If condition parameter is taken as input from GUI." */
      /*SAFETYMCUSW 1 J MR:14.1 <APPROVED> "If condition parameter is taken as input from GUI." */
      EMACRxDisable(hdkif->emac_base);
      EMACRxIntPulseDisable(hdkif->emac_base, hdkif->emac_ctrl_base, 0x00, (uint32)EMAC_CHANNELNUMBER);
#endif

return retVal;
}

/**
* This function should do the actual transmission of the packet. The packet is
* contained in the pbuf that is passed to the function. This pbuf might be
* chained. That is, one pbuf can span more than one tx buffer descriptors
*
* @param hdkif network interface structure
* @param pbuf the pbuf structure which contains the data to be sent using EMAC
* @return boolean.
*        -Returns FALSE if a Null pointer was passed for transmission
*        -Returns TRUE if valid data is sent and is transmitted.
*/
/* SourceId : ETH_SourceId_050 */
/* DesignId : ETH_DesignId_050*/
/* Requirements : HL_ETH_SR31 */
boolean EMACTransmit(hdkif_t *hdkif, pbuf_t *pbuf)
{

txch_t *txch;
pbuf_t *q;
uint16 totLen;
uint16 qLen;
volatile emac_tx_bd_t *curr_bd,*active_head, *bd_end;
boolean retValue = FALSE;
if((pbuf != NULL) && (hdkif != NULL))
{
txch = &(hdkif->txchptr);

/* Get the buffer descriptor which is free to transmit */
/*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
curr_bd = txch->free_head;
/*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
bd_end = curr_bd;
/*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
active_head = curr_bd;

/* Update the total packet length */
/*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
curr_bd->flags_pktlen &= (~((uint32)0xFFFFU));
/*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
totLen = pbuf->tot_len;
curr_bd->flags_pktlen |= (uint32)(totLen);

/* Indicate the start of the packet */
/*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
curr_bd->flags_pktlen |= (EMAC_BUF_DESC_SOP | EMAC_BUF_DESC_OWNER);

/* Copy pbuf information into TX buffer descriptors */
    q = pbuf;
    while(q != NULL)
    {
    /* Initialize the buffer pointer and length */
    /*SAFETYMCUSW 439 S MR:11.3 <APPROVED> "RHS is a pointer value required to be stored. - Advisory as per MISRA" */
    /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
    curr_bd->bufptr = (uint32)(q->payload);
    /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
    qLen = q->len;
    curr_bd->bufoff_len = ((uint32)(qLen) & 0xFFFFU);
    /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
    bd_end = curr_bd;
    /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
    curr_bd = curr_bd->next;
    q = q->next;
    }

/* Indicate the start and end of the packet */
/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
/*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
bd_end->next = NULL;
/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
bd_end->flags_pktlen |= EMAC_BUF_DESC_EOP;

/*SAFETYMCUSW 71 S MR:17.6 <APPROVED> "Assigned pointer value has required scope." */
txch->free_head = curr_bd;

/* For the first time, write the HDP with the filled bd */
if(txch->active_tail == NULL) {
    /*SAFETYMCUSW 439 S MR:11.3 <APPROVED> "Address stored in pointer is passed as as an int parameter. - Advisory as per MISRA" */
    /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
    EMACTxHdrDescPtrWrite(hdkif->emac_base, (uint32)(active_head), (uint32)EMAC_CHANNELNUMBER);
}

/*
   * Chain the bd's. If the DMA engine, already reached the end of the chain,
   * the EOQ will be set. In that case, the HDP shall be written again.
   */
else {
    /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
    curr_bd = txch->active_tail;
    /* Wait for the EOQ bit is set */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
    /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
    while (EMAC_BUF_DESC_EOQ != (curr_bd->flags_pktlen & EMAC_BUF_DESC_EOQ))
    {
    }
    /* Don't write to TXHDP0 until it turns to zero */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
    while (((uint32)0U != *((uint32 *)0xFCF78600U)))
    {
    }
    /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
    curr_bd->next = active_head;
    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
    /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
    if (EMAC_BUF_DESC_EOQ == (curr_bd->flags_pktlen & EMAC_BUF_DESC_EOQ)) {
      /* Write the Header Descriptor Pointer and start DMA */
      /*SAFETYMCUSW 439 S MR:11.3 <APPROVED> "Address stored in pointer is passed as as an int parameter. - Advisory as per MISRA" */
      /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
      EMACTxHdrDescPtrWrite(hdkif->emac_base, (uint32)(active_head), (uint32)EMAC_CHANNELNUMBER);
    }
}

/*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
txch->active_tail = bd_end;
retValue = TRUE;
}
else
{
    retValue = FALSE;
}
return retValue;
}

/**
* Function for processing Tx buffer descriptors.
*
* @param hdkif interface structure
* @return none
*/
/* SourceId : ETH_SourceId_051 */
/* DesignId : ETH_DesignId_051*/
/* Requirements : HL_ETH_SR15 */
void EMACTxIntHandler(hdkif_t *hdkif)
{
txch_t *txch_int;
volatile emac_tx_bd_t *curr_bd, *next_bd_to_process;

txch_int = &(hdkif->txchptr);

/*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
next_bd_to_process = txch_int->next_bd_to_process;

/*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
curr_bd = next_bd_to_process;

/* Check for correct start of packet */
/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
/*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
while(((curr_bd->flags_pktlen) & EMAC_BUF_DESC_SOP) == EMAC_BUF_DESC_SOP) {

    /* Make sure that the transmission is over */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
    /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
    while(((curr_bd->flags_pktlen) & EMAC_BUF_DESC_OWNER) == EMAC_BUF_DESC_OWNER)
    {
    }

    /* Traverse till the end of packet is reached */
    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
    /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
    while(((curr_bd->flags_pktlen) & EMAC_BUF_DESC_EOP) != EMAC_BUF_DESC_EOP) {
       curr_bd = curr_bd->next;
    }

    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
    /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
    next_bd_to_process->flags_pktlen &= ~(EMAC_BUF_DESC_SOP);
    /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
    curr_bd->flags_pktlen &= ~(EMAC_BUF_DESC_EOP);

    /**
     * If there are no more data transmitted, the next interrupt
     * shall happen with the pbuf associated with the free_head
     */
      /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
    if(curr_bd->next == NULL) {
      /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
      txch_int->next_bd_to_process = txch_int->free_head;
    }

    else {
      /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
      txch_int->next_bd_to_process = curr_bd->next;
    }

    /* Acknowledge the EMAC and free the corresponding pbuf */
    /*SAFETYMCUSW 439 S MR:11.3 <APPROVED> "Address stored in pointer is passed as as an int parameter. - Advisory as per MISRA" */
    /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
    /*SAFETYMCUSW 344 S MR:11.5 <APPROVED> "Address stored in pointer is passed as as an int parameter." */
    EMACTxCPWrite(hdkif->emac_base, (uint32)EMAC_CHANNELNUMBER, (uint32)curr_bd);
    /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
    next_bd_to_process = txch_int->next_bd_to_process;
    /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
    curr_bd = next_bd_to_process;

}

}

/**
* Function for processing received packets.
*
* @param hdkif interface structure
* @return none
*/
/* SourceId : ETH_SourceId_052 */
/* DesignId : ETH_DesignId_052*/
/* Requirements : HL_ETH_SR31 */
void EMACReceive(hdkif_t *hdkif)
{
rxch_t *rxch_int;
volatile emac_rx_bd_t *curr_bd, *curr_tail, *last_bd;

/* The receive structure that holds data about a particular receive channel */
rxch_int = &(hdkif->rxchptr);

/* Get the buffer descriptors which contain the earliest filled data */
/*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
curr_bd = rxch_int->active_head;
/*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
last_bd = rxch_int->active_tail;

/**
   * Process the descriptors as long as data is available
   * when the DMA is receiving data, SOP flag will be set
*/
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
/*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
while((curr_bd->flags_pktlen & EMAC_BUF_DESC_SOP) == EMAC_BUF_DESC_SOP) {

    /* Start processing once the packet is loaded */
    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
    /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
    if((curr_bd->flags_pktlen & EMAC_BUF_DESC_OWNER)
       != EMAC_BUF_DESC_OWNER) {

      /* this bd chain will be freed after processing */
      /*SAFETYMCUSW 71 S MR:17.6 <APPROVED> "Assigned pointer value has required scope." */
      /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
      rxch_int->free_head = curr_bd;

      /* Get the total length of the packet. curr_bd points to the start
       * of the packet.
       */

      /*
       * The loop runs till it reaches the end of the packet.
       */
      /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
      /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
      while((curr_bd->flags_pktlen & EMAC_BUF_DESC_EOP)!= EMAC_BUF_DESC_EOP)
      {
        /*Update the flags for the descriptor again and the length of the buffer*/
      /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
        curr_bd->flags_pktlen = (uint32)EMAC_BUF_DESC_OWNER;
      /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
        curr_bd->bufoff_len = (uint32)MAX_TRANSFER_UNIT;
      /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
        last_bd = curr_bd;
      /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
        curr_bd = curr_bd->next;
      }

      /* Updating the last descriptor (which contained the EOP flag) */
      /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
        curr_bd->flags_pktlen = (uint32)EMAC_BUF_DESC_OWNER;
      /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
        curr_bd->bufoff_len = (uint32)MAX_TRANSFER_UNIT;
      /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
        last_bd = curr_bd;
      /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
        curr_bd = curr_bd->next;

      /* Acknowledge that this packet is processed */
      /*SAFETYMCUSW 439 S MR:11.3 <APPROVED> "Address stored in pointer is passed as as an int parameter. - Advisory as per MISRA" */
      /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
      EMACRxCPWrite(hdkif->emac_base, (uint32)EMAC_CHANNELNUMBER, (uint32)last_bd);

      /* The next buffer descriptor is the new head of the linked list. */
      /*SAFETYMCUSW 71 S MR:17.6 <APPROVED> "Assigned pointer value has required scope." */
      /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
      rxch_int->active_head = curr_bd;

      /* The processed descriptor is now the tail of the linked list. */
      /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
      curr_tail = rxch_int->active_tail;
    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
      /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
      curr_tail->next = rxch_int->free_head;

      /* The last element in the already processed Rx descriptor chain is now the end of list. */
      /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
      /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
      last_bd->next = NULL;

        /**
         * Check if the reception has ended. If the EOQ flag is set, the NULL
         * Pointer is taken by the DMA engine. So we need to write the RX HDP
         * with the next descriptor.
         */
        /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
        /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
      /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
        if((curr_tail->flags_pktlen & EMAC_BUF_DESC_EOQ) == EMAC_BUF_DESC_EOQ) {
          /*SAFETYMCUSW 439 S MR:11.3 <APPROVED> "Address stored in pointer is passed as as an int parameter. - Advisory as per MISRA" */
          /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
          EMACRxHdrDescPtrWrite(hdkif->emac_base, (uint32)(rxch_int->free_head), (uint32)EMAC_CHANNELNUMBER);
        }

        /*SAFETYMCUSW 71 S MR:17.6 <APPROVED> "Assigned pointer value has required scope." */
        /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
        /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
        rxch_int->free_head = curr_bd;
        rxch_int->active_tail = last_bd;
      }
    }
}

/** @fn void EMACGetConfigValue(emac_config_reg_t *config_reg, config_value_type_t type)
*   @brief Get the initial or current values of the configuration registers
*
*   @param[in] *config_reg: pointer to the struct to which the initial or current
*                           value of the configuration registers need to be stored
*   @param[in] type:    whether initial or current value of the configuration registers need to be stored
*                       - InitialValue: initial value of the configuration registers will be stored
*                                       in the struct pointed by config_reg
*                       - CurrentValue: initial value of the configuration registers will be stored
*                                       in the struct pointed by config_reg
*
*   This function will copy the initial or current value (depending on the parameter 'type')
*   of the configuration registers to the struct pointed by config_reg
*
*/
/* SourceId : ETH_SourceId_053 */
/* DesignId : ETH_DesignId_053*/
/* Requirements : HL_ETH_SR52 */
void EMACGetConfigValue(emac_config_reg_t *config_reg, config_value_type_t type)
{
    if (type == InitialValue)
    {
        config_reg->TXCONTROL = EMAC_TXCONTROL_CONFIGVALUE;
        config_reg->RXCONTROL = EMAC_RXCONTROL_CONFIGVALUE;
        config_reg->TXINTMASKSET = EMAC_TXINTMASKSET_CONFIGVALUE;
        config_reg->TXINTMASKCLEAR = EMAC_TXINTMASKCLEAR_CONFIGVALUE;
        config_reg->RXINTMASKSET = EMAC_RXINTMASKSET_CONFIGVALUE;
        config_reg->RXINTMASKCLEAR = EMAC_RXINTMASKCLEAR_CONFIGVALUE;
        config_reg->MACSRCADDRHI = EMAC_MACSRCADDRHI_CONFIGVALUE;
        config_reg->MACSRCADDRLO = EMAC_MACSRCADDRLO_CONFIGVALUE;
        config_reg->MDIOCONTROL = EMAC_MDIOCONTROL_CONFIGVALUE;
        config_reg->C0RXEN = EMAC_C0RXEN_CONFIGVALUE;
        config_reg->C0TXEN = EMAC_C0TXEN_CONFIGVALUE;
    }
    else
    {
        config_reg->TXCONTROL = HWREG(EMAC_0_BASE + EMAC_TXCONTROL);
        config_reg->RXCONTROL = HWREG(EMAC_0_BASE + EMAC_RXCONTROL);
        config_reg->TXINTMASKSET = HWREG(EMAC_0_BASE + EMAC_TXINTMASKSET);
        config_reg->TXINTMASKCLEAR = HWREG(EMAC_0_BASE + EMAC_TXINTMASKCLEAR);
        config_reg->RXINTMASKSET = HWREG(EMAC_0_BASE + EMAC_RXINTMASKSET);
        config_reg->RXINTMASKCLEAR = HWREG(EMAC_0_BASE + EMAC_RXINTMASKCLEAR);
        config_reg->MACSRCADDRHI = HWREG(EMAC_0_BASE + EMAC_MACSRCADDRHI);
        config_reg->MACSRCADDRLO = HWREG(EMAC_0_BASE + EMAC_MACSRCADDRLO);
        config_reg->MDIOCONTROL = HWREG(MDIO_0_BASE + MDIO_CONTROL);
        config_reg->C0RXEN = HWREG(EMAC_CTRL_0_BASE + EMAC_CTRL_CnRXEN(0U));
        config_reg->C0TXEN = HWREG(EMAC_CTRL_0_BASE + EMAC_CTRL_CnTXEN(0U));
    }

}

/* ISR for EMAC Transmit Interrupt. Calls another handler function for processing the descriptors.
*
* @return none
* */
/*SAFETYMCUSW 69 S MR:3.4 <APPROVED> "#pragma required for interrupt handler." */
#pragma CODE_STATE(EMACTxIntISR, 32)
/*SAFETYMCUSW 69 S MR:3.4 <APPROVED> "#pragma required for interrupt handler." */
#pragma INTERRUPT(EMACTxIntISR, IRQ)
/* SourceId : ETH_SourceId_054 */
/* DesignId : ETH_DesignId_054*/
/* Requirements : HL_ETH_SR15,HL_ETH_SR33 */
void EMACTxIntISR(void)
{
    hdkif_t *hdkif;
    hdkif= &hdkif_data[0U];
    /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
    /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
    /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
    /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
    /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
    /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
    emacTxNotification(hdkif);
    /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
    /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
    /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
    EMACTxIntHandler(hdkif);
    EMACCoreIntAck(hdkif->emac_base, (uint32)EMAC_INT_CORE0_TX);
    TestTx++;

}

/**
* ISR for Receive interrupt. Calls another function for processing the received packets.
*
* @return none
*/
/*SAFETYMCUSW 69 S MR:3.4 <APPROVED> "#pragma required for interrupt handler." */
#pragma CODE_STATE(EMACRxIntISR, 32)
/*SAFETYMCUSW 69 S MR:3.4 <APPROVED> "#pragma required for interrupt handler." */
#pragma INTERRUPT(EMACRxIntISR, IRQ)
/* SourceId : ETH_SourceId_055 */
/* DesignId : ETH_DesignId_055*/
/* Requirements : HL_ETH_SR15,HL_ETH_SR33 */
void EMACRxIntISR(void)
{
    hdkif_t *hdkif;
    hdkif= &hdkif_data[0U];
    /* The data is received in the allocated receive descriptors starting from (&(hdkif->rxchptr))->active_head */
    /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
    /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
    /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
    /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
    /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
    /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
    emacRxNotification(hdkif);
    /* In this function, the filled receive buffer descriptors are freed for further usage and the receive interrupt is acknowledged. */
    /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
    /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
    /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are assigned in this driver" */
    EMACReceive(hdkif);

    /* Acknowledge the EMAC Core Rx Interrupts */
    EMACCoreIntAck(hdkif->emac_base, (uint32)EMAC_INT_CORE0_RX);
    TestRx++;
}

/* USER CODE BEGIN (2) */
/* USER CODE END */

/***************************** End Of File ***********************************/

0 Shruthi Gurunath66 over 6 years ago in reply to Shruthi Gurunath66

Intellectual 360 points

The code above is working only for Tx ISR, but Rx ISR is not coming at all.. All suggestions from the group are tried out. Please check the code.

0 QJ Wang over 6 years ago in reply to Shruthi Gurunath66

TI__Guru**** 196296 points

Hello,

I did a test with HALCOGen generated code, it works fine.

1. In HALCoGen, uncheck "Enable Loopback Communication" in EMAC configuration panel
2. Configure Pinmux, clock (VCLK4=40MHz), VIM (77, 79)
3. Generate code, then add following code to main()

int main(void)
{
/* USER CODE BEGIN (3) */
_enable_IRQ();
EMACHWInit(emacAddress);
create_packet();
EMACTransmit(&hdkif_data[0], &pack[0]);

//check if pbuf_array at 0x08001500 match with data at 0x08005024
//pbuf_array is rxed data
//data is the payload txed
while(1);
}

4. At RJ-45, route TX to RX (it's better to use a adaptor)
5. run the code, then check the payload: data as txed, pay_array is rxed

So if your HW connection between Launchpad and PHY, and RJ-45 connector, you should get the RX data using the HALCOGen code.

0 Shruthi Gurunath66 over 6 years ago in reply to QJ Wang

Intellectual 360 points

Hello Wang,

I unchecked Enable Loopback Communication from halcogen. The code is not going to EMACRxIntISR, hence 0x08001500 is not same as 08005024, pbuf_array is showing zeros. PINMUX PINMMR also checked from the document as in controlling of MII Signals. Enabled the interrupt also.

0 Shruthi Gurunath66 over 6 years ago in reply to Shruthi Gurunath66

Intellectual 360 points

ETHERNET_TEST2.rar

0 Shruthi Gurunath66 over 6 years ago in reply to Shruthi Gurunath66

Intellectual 360 points

Hi Wang,

Please see the hardware connection schematic between lauchpad and PHY. But we have not connected RJ-45. Since we enabled loopback in PHY itself.TXD[3:0] and RXD[3:0] signals are appearing on PHY PINS. But Rx Interrupt is not coming at all. Please check sys_main.c

0 QJ Wang over 6 years ago in reply to Shruthi Gurunath66

TI__Guru**** 196296 points

Hello Shruthi,

As I said, if the connection between EMAC and PHY, and RJ45 (plus magnetic) are correct, the HALCoGen generated EMAC drive will work without any issue.

For external loopback, you need connect pin 1 to pin 3, and pin 2 to pin 6 of RJ45.

0 Shruthi Gurunath66 over 6 years ago in reply to QJ Wang

Intellectual 360 points

Hi Wang,

Tried the way in which it is told by you. Then also Rx Interrupt is not coming.

0 Shruthi Gurunath66 over 6 years ago in reply to Shruthi Gurunath66

Intellectual 360 points

Hi Wang,

Finally We could get the interrupt and receiving data in buffer address. Thank you for all your suggestions.

Arm-based microcontrollers

Arm-based microcontrollers forum

CCS: RM46L852 LAUNCHPAD AND DP83640 PHY