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When to use hibernate vs. sleep?

Nipun Gunawardena
Intellectual 585 points

Hi all,

When is the best time to use hibernate modes of the Tiva microcontrollers vs. the sleep modes? If you use hibernate, the current consumption is ridiculously low, but programming becomes more difficult since the content in ram is lost. Programming deep sleep is easier, but the current consumption is high when compared to the hibernate modes.

For example, in my application, I've configured the processor to wake up from hibernate once every 10 seconds to gather and transmit some sensor measurements. When the processor is hibernating, I've measured a 7uA current draw (which is awesome!), but I don't know if there is a high current draw associated with the startup process that negates the hibernate time. Is ten seconds to short for a hibernate time and would I better off trying to get the deep sleep modes working well? Also, is the 600uA deep sleep current draw specified here (http://www.ti.com/lit/wp/spmy010/spmy010.pdf) accurate?

I'm sorry if this is a very basic question, it's just a design consideration I haven't seen much documentation about. Thanks in advance for any help!

- NG 

  • 0
    TI__Guru**** 244400 points

    Hello Nipun,

    Let us clarify a few points here.

    1. The user application code is stored in Flash and it is the responsibility of the code to ensure that the device is initialized. This would be akin to having a fresh part and downloading executing a code. But with Flash the code once downloaded will continue to stay/

    2. Of course hibernate gives lower current compared to deep sleep. The condition normally used to make this decision is how long will the uC stay in this state v/s any active state and then compute the mW consumption per second for different mode. Hibernate requires a full rebot which takes ~10ms during which current would be in few 10's of mA. If there is substantial saving in mW per sec for Deep Sleep compared to Hibernate then use Deep Seep, else hibernate.

    The data sheet in the electrical section -> current consumption sub section specifies the current in different modes. The current can be dropped further by scaling down the Core Voltage of 1.2V to 0,9V and would be in the ball park of ~600uA for TM4C123.

    Regards

    Amit

  • 0 in reply to Amit Ashara
    Intellectual 585 points

    Hi Amit,

    Thank you very much for your quick response, that addressed all of my questions! Marked as answered.

    - NG 

  • 0 in reply to Amit Ashara
    Guru 27285 points

    Amit Ashara said:
    The current can be dropped further by scaling down the Core Voltage of 1.2V to 0,9V

     Hi Amit, how this can be done? Core regulator is internal to chip and I seen nothing reporting internal VCore regulation or selection. Is this an undocumented feature?

     MSP430 in case of very low power never can be bet by. These processor are very fast but MSP is very ULTRA low power and awakening in a bare uS

  • 0 in reply to Roberto Romano
    TI__Guru**** 244400 points

    Hello Roberto,

    In the SYSCTL peripheral there is LDOSPCTL and LDODPCTL, which can be used to over-ride the LDO voltage of 1.2V to a lower or higher voltage. When scaling down the voltage it is important to know that 80MHz would not be useful but only up to 20MHz can be used as the fastest clock.

    Regards

    Amit