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CCP Timer Configuration

KM01
Intellectual 295 points


Hello,

I am attempting to setup up two input captures. Both channels utilize Timer5 CCP. Therefore, I use the split timer and assign Timer A and Timer B, respectively to the appropriate pin. I use edge detection and jump to the appropriate ISR when a single edge is detected. I was able to get my code to work correctly when I configured just T5CCP0 (Timer A). However, when I add in the T5CCP1 (Timer B) configuration to my code, it appears that which ever timer was configured most recently is the one that functions and the other timer no longer captures events. -- I tried swapping the order they are initialized and found this trend. They both work independently. Do I have a bug in my initialization of my timers that is causing one channel to be masked?

Thank you.

ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER5);
ROM_GPIOPinTypeTimer(GPIO_PORTM_BASE, GPIO_PIN_2);
ROM_GPIOPinTypeTimer(GPIO_PORTM_BASE, GPIO_PIN_3);
ROM_GPIOPinConfigure(GPIO_PM2_T5CCP0);
ROM_GPIOPinConfigure(GPIO_PM3_T5CCP1);

ROM_IntMasterEnable();
ROM_TimerConfigure(TIMER5_BASE, (TIMER_CFG_SPLIT_PAIR | TIMER_CFG_A_CAP_COUNT));
ROM_TimerConfigure(TIMER5_BASE, (TIMER_CFG_SPLIT_PAIR | TIMER_CFG_B_CAP_COUNT));

ROM_TimerLoadSet(TIMER5_BASE, TIMER_A, 1);
ROM_TimerMatchSet(TIMER5_BASE, TIMER_A, 0);
ROM_TimerLoadSet(TIMER5_BASE, TIMER_B, 1);
ROM_TimerMatchSet(TIMER5_BASE, TIMER_B, 0);


ROM_TimerControlEvent(TIMER5_BASE, TIMER_A, TIMER_EVENT_NEG_EDGE);
ROM_TimerControlEvent(TIMER5_BASE, TIMER_B, TIMER_EVENT_POS_EDGE);

ROM_TimerIntEnable(TIMER5_BASE, TIMER_CAPA_MATCH);
ROM_TimerIntEnable(TIMER5_BASE, TIMER_CAPB_MATCH);

ROM_TimerEnable(TIMER5_BASE, TIMER_A);
ROM_TimerEnable(TIMER5_BASE, TIMER_B);

ROM_IntEnable(INT_TIMER5A);
ROM_IntEnable(INT_TIMER5B);

  • 0
    TI__Guru**** 244400 points
    Hello KM01,

    Can you please use TIMER_BOTH when enabling the timers. There is a similar bug reported by Luis Afonso on the forum and this shall be addressed in the next TivaWare release. In the meantime you can copy the Configuration registers of the working one to the non-working sub timer.

    Regards
    Amit
  • 0 in reply to Amit Ashara
    Intellectual 295 points
    Amit, thank you for the reply. Is there an expected date for the next TivaWare release?
  • 0 in reply to KM01
    TI__Guru**** 244400 points
    Hello KM01

    Not yet, as bug fixes have to be evaluated and tested before a release and this will take time.

    Regards
    Amit
  • 0 in reply to Amit Ashara
    Intellectual 780 points
    Looking at the code in the beginning of this post, are you able to configure timer A as a 32-bit instead of 16-bit. It seems like I've tried every combination and I never enter the interrupt. It sees like you should be able to configure the timer like I did below but it doesn't seem to work. Every example in TivaWare always uses TIMER_CFG_SPLIT_PAIR which sets the timer up as 16-bit.

    ROM_TimerConfigure(TIMER5_BASE, TIMER_CFG_A_CAP_COUNT);
  • 0 in reply to Kelly Meemken
    TI__Guru**** 244400 points
    Hello Kelly,

    The parameter TIMER_CFG_SPLIT_PAIR is required for configuring the half width timers.

    Regards
    Amit
  • 0 in reply to Amit Ashara
    Intellectual 780 points
    by half width timers do you mean 16-bit? Can't I configure Timer5 as a 32-bit?
  • 0 in reply to Kelly Meemken
    TI__Guru**** 244400 points
    Hello Kelly,

    All timers can be configured for either 16 bit or 32 bit mode. However Count mode is available only in 16 bit mode.

    Regards
    Amit
  • 0 in reply to Amit Ashara
    Guru 56033 points

    Hi Amit,

    Recall some one else long ago reported a similar CCP interrupt issue months ago posts regarding a fan taco reading. As luck would have it the very same issues during (Back Tracking) came up today. It was discovered Tivaware disables both timers configuring timer A-CCP0 that was being disabled a second time when configuring timer B CCP1. The fix was to only disable the timer that is being configured so later configuration on the same timer does not undo what was previously done.

    Was configuring TMB in edge count event interrupt mode and TMA for PWM rising edge match count interrupt events. The outcome was it looked like interrupts were disabled by the alternate timer.

    So as it now appears 2 independent 16 bit timer interrupts can exist for the CCP function in a single timer.

    https://e2e.ti.com/support/microcontrollers/tiva_arm/f/908/p/464429/1673151#1673151

    e2e.ti.com/.../471775

  • 0 in reply to Genatco
    TI__Guru**** 244400 points
    Hello BP101,

    When configuring the timers, the two have to be configured together with the SPLIT_PAIR macro definition.

    Regards
    Amit
  • 0 in reply to Amit Ashara
    Guru 56033 points

    Hi Amit,

    Noted spit pair macro call was first in line in both TM5A/B configurations and the long story moved capture interrupt to a new timer TM4B.
    The odd thing is the issue encountered with enabling TM5A/B CCP0/1 for dual interrupts is not occurring with TM0A/B by calling the same individual HW Macro TM5A/B enables for the configurations in the post links above.

    Oddly the PWM TM5A was enabled & modulating the CCP0 pin but the event capture interrupt was not triggering after the second TM5B edge count match interrupt CPP1 was enabled. The only difference at (that time) was the edge count TM5B was in count up mode and both were not set for edge count as KM01 poster shows. Later the edge count CCP1 pin was stressed so we switched over to TM4B CCP1 down count edge count match interrupt and TM5A PWM CCP0 interrupt mysteriously started working.

    Our PCB is planned to use TM5A/B but now considering to move fan PWM/Taco pin traces over to TM0A/B (verified) working together.

    Have to wonder has there been errata issues with TM5A/B interrupts when configured in edge count match and PWM event capture modes?

  • 0 in reply to Genatco
    Guru 56033 points

    Hi Amit,

    Testing another TM4C1294i3 launch pad; TM5A is working with the PWM capture (Event) interrupt CAEIM a later choice with TM5B interrupt CBMIM. Initially we were using the TM5A in PWM capture mode (Match) interrupt CAMIM. At that time TM5A capture mode Match CAMIM was vectoring ok for PWM down count CPP Events until enabling the CBMIM then the PWM interrupt stopped vectoring.

    That (CAMIM) may be an illegal interrupt mode for the Split Pair timer when only one half is set in PWM mode???? Yet the function call reload count value is named TimerMatchSet() making it seem a legal call for the PWM capture mode Match interrupt.

    The datasheet does not state Match or Event interrupt mode is specific to a timers configuration but it seems the capture mode Event (CnEIM) interrupt is only legal with PWM in a split pair configuration.

    Perhaps Tivaware SW library should include a (TimerEventSet()) function call for the PWM capture mode event interrupt! 

    ROM_TimerMatchSet(TIMER5_BASE, TIMER_A,  g_ui32FanDutyCycle / ui32PWMDutyUpdate);