PWM clock jitter may inflict dead band edge timing at short pwmA pulse widths.

>What is the minimum on time required for your power circuit?

That which is not specified in the electrical characteristics is assumed the minimum pulse width SW constraint for dead band. The only warning given "Be careful not to send to short a pulse into dead band pwmA ." That statement gives no electrical timing reason why pwmA must be kept above some imaginary value in dead band generators as nobody knows the range of timing limitations.

For example to maintain 800ns min-pulse width in the high voltage inverter phase drive, PWM0 pwmA input pulse width into DB generator might require a total pulse width of 1.250us though the actual dead band (delay) pulse produced is fixed at 180ns by the PWMnDBRISE register value. That infers some kind of pulse width subtraction (propagation loss) but what are input edge time to output edge time min/max values the silicon can tolerate without SW forcing limitation in the delay timer counter of DB generator?

An electrical specification is necessary to account for any PWM clock jitter. That directly effects pwmA producing somewhat random edge timing events in the relative process of also producing (SW constrained) dead band delay pulses in the PWM pin drives. Otherwise might end up producing the SW constraint right against an earthquake shaking wall before it crashes. Point is we need to stay back from the (imaginary) wall and simply watch it shake not get taken down by it.

BP101 said:

>As for the incomprehensible text, I'm gathering that you neither know nor enforce the required minimum pulse widths of your power electronics. That likely explains a lot of your problems

The minimum pulse width (off time) is enforced during generator global synch updates and dead band local sync updates on zero counts. It seems when the duty cycle (pwmA) nears 95% the minimum pulse width remains static (pwmB) over 1.1us derived from 240ns dead band setting, even after hours of operation may suddenly have a shoot through and may simply panic or even blow fuse. ...

So you don't know the minimum pulse width required by the power electronics.

Robert

>So you don't know the minimum pulse width required by the power electronics.

Has little to do with the inverter off time and a whole lot more to do with dead band warning first post. 

There seems to be a minimum (undocumented) number of PWM clocks for set up and width any pulse sent into dead band relative to duty cycle. Again one can only know what that number is when duty cycle hits 98% and by periodic crashing dead band. Again that behavior may be similar errata #10 LM3S8971. Thus LMI jamming CMPB only complicated the issue as pwmA had no dead band pulses what so ever and relied on static pulse width pwmB to provide a perpetual delay low as 40ns. Have learned via research the LM3S dead band had issues to begin with and new unexpected timing gremlin's were playing games TM4C.

That behavior somewhat avoided TM4C dead band pwmA now produces RED added to (high) pulse width and as noted directly reduces the minimum (low) pulse time in the duty cycle. Example; PWMnDBCTRL register writes asserts may have timing limitations relative to PWM clocks, dead band counter load setup time and or maximum duty cycle percent where the RED pulse is not ever passed. Hard to imagine any timing constraint when PWM clock 60Mhz and the modulation frequency only 12.5Khz, 80us periods.

Still believe any added PWM clock jitter directly changes the (moving) edge times in dead band 10 bit counters. Obviously there is a minimum safe timing though efficiency may suffer keeping to far above the minimum yet below the maximum. Especially true as the pulse width pwmA is constantly changing to account for ADC samples indicating phase current load and PI controller speed corrections.   

The data sheet really needs to disclose dead band timing diagrams relative to PWM clocks to the electrical characteristics!

BP101 said:

>So you don't know the minimum pulse width required by the power electronics.

Has little to do with the inverter off time and a whole lot more to do with dead band warning first post. 

It has everything to do with the minimum pulse widths of the power electronics. That is what the warning in the data sheet is saying. You must take the deadband into account when you are ensuring the minimum pulse widths. If not you will get too narrow pulse widths.

Robert

>If not you will get too narrow pulse widths.

One would honestly believe that case yet what actually occurs is no RED pulse is produced and the output of dead band generator remains true until the next off cycle. The point is pwmA puse width is always kept well above the value of PWMnDBRISE/FALL so the warning does not apply to what is occuring.

The preset minimum pulse width 400ns + DBRISE/FALL 200ns = 600ns + trim 370ns sets minimum near 970ns. The FET on time under extreme load could reach 78us keeping well with in SOA 100us near 60amps. Yet when random faults occurred there was no extreme rotor load and current was near 6.8 amps RMS at +70vdc.  

A bit more trim seems to have stopped false panics and blown fuses even under fairy heavy rotor loads with 970ns minimum pulse. The edge position dead band delay seems a bit critical and expect speed jitter being inverter DC unregulated and follows AC line changes +/- 1-2v at times. Recently moved it up to +100v and all seems well 970ns though past run target was +150v and hope same luck prevails. How  the minimum pulse ever worked with persistent FED dead band 120ns pwmB LM3S leaves me baffled. Fact is the same minimum pulse effects both pwmA/B and TM4C now has RED pulses on pwmA included into the duty cycle updates the LM3S never had and quickly became uncharted no mans land.

BP101 said:

>If not you will get too narrow pulse widths.

One would honestly believe that case yet what actually occurs is no RED pulse is produced

You've made similar claims before and have yet to provide a test case.

No one is going to believe you until you do.

And you apparent inability to determine the minimum pulse width of your power electronics is quite sufficient to explain the symptoms you complain of.

Robert

>And you apparent inability to determine the minimum pulse width

Perhaps you didn't understand SOA (100us) is the bullet you refer to and 80us period (100% duty) most conservative maintains a 20us safety margin. Besides the FET data sheet  ECL claims 100ns blocking (dead band). So 970ns minimum off time pwmB produces roughly 400ns IDS on time pulse before dead band randomly adds 200ns delay to pwmA minimum pulse during FET switch off ever PWM nears 100% duty.

Point is a minimum dead band pulse width must be maintained above PWMnDBRISE/FALL value and that is not being disclosed in the data sheet. Simply stating pwmA pulse width should be kept above the value DBRISE/FALL at all times is no explanation that can translate into any kind of safety margin.

There obviously is an undocumented setup/settling time requirement for dead band generators valid output state upon asserting rapid PWMnDBCTRL enable/disable in local updates. That dead band setup time or SW control to enable seemingly ends up being roughly 21 PWM clocks (350ns). Be nice for TI lab engineers to investigate update data sheet with some real facts. Leaving PWNnDBCTRL enable bit set persistently during PWM control block local update output cycles is not an option an never was for (FOC) commutation cycles.   

BP101 said:

>And you apparent inability to determine the minimum pulse width

Perhaps you didn't understand SOA (100us) is the bullet you refer to

Bullet?

Equating SOA with a time is non-nonsensical in this context (I suspect you may be thinking of transient thermal response which has nothing to do with minimum pulse width requirements).

Oh, and this is the first time you have brought any of this up.

BP101 said:

Besides the FET data sheet  ECL claims 100ns blocking (dead band).

Um, what? Try actually quoting the datasheet because your paraphrase makes no sense. Are you maybe referring to the integral body diode's reverse recovery time? If so you are still missing the point.

BP101 said:

Point is a minimum dead band pulse width must be maintained above PWMnDBRISE/FALL value and that is not being disclosed in the data sheet.

That is a assertion w/o evidence. I don't believe it's referring to any such thing.

Try again to determine the minimum pulse width required by your power electronics.

Robert

BP101 said:

>Equating SOA with a time is non-nonsensical in this context (I suspect you may be thinking of transient thermal response which has nothing to do with minimum pulse width requirements).

Perhaps an incorrect assumption on your part

No assumption, wild speculation given the lack of any indication of what you were talking about.

BP101 said:

Basically the inverse to SOA single pulse test time becomes the minimum off time gauge relative to blocking time in dead band.

No.

BP101 said:

> Are you maybe referring to the integral body diode's reverse recovery time? If so you are still missing the point.

Nope I^R actually lists the minimum blocking time for DS turn off as 100ns.

OK, that gave me a place to start. It appears to be a parameter peculiar to Infineon and I haven't been able to find an actual definition of it. I did finally find a a whitepaper that may reference it and if it was that paper suggests (it appears to be related to switching between the freewheel diode and the resistive path provided by the FET) then it is a piece of the deadband requirements.  It is not, however the minimum pulse width.

If you have a reference to the definition I'd like to see it.

BP101 said:

>That is a assertion w/o evidence. I don't believe it's referring to any such thing.
The evidence is the vendor has not provided a timing value for the claim being made in datasheet and posted in this thread.

You have a poor appreciation of the word evidence.

BP101 said:

>Try again to determine the minimum pulse width required by your power electronics.

First of all that is a constraint of gate off time which effects the PWM pulse width modulators ability to proved such a short off time when dead band generators and local updates are occurring in other generators. The user parameter limits any single off pulse 100ns + padding mentioned earlier and 0.8us was producing 1.1us phase pulse when random faulting near 98% duty cycle. Now set 0.4us user parameter producing average 970ns phase pulse steady state so even shorter with no issues after adding more padding however the duty cycle is now much wider at 100v than it was at 80v more padding seemed to help.

That appears completely unrelated to the question, although it's not comprehensible enough to be sure.

BP101 said:

The PWM duty cycle and dead band have a non disclosed timing margin that must be maintained or there is a PWM crash if ever the edges some how overlap.

So you keep asserting w/o evidence.

BP101 said:

Maximum 79.9us FET gate on time leaves 100ns minimum off time + dead delay.

That seems rather small.

Robert