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Launch Pad Booster Pack Cross reference SSI

Work in progress to be updated till final version better on stiki and can help solve increasing demand on forum.

 Port A assignment signal has different behaviour, 129 support full SD multibit serial transfer, pin got new name and in legacy mode

PA4  SSI RX on 123 series is assigned to PA5 on 129 DAT1

PA5  SSI TX on 123 series is assigned to PA4 on 129 DAT0

 No issue are on pin of port A of launchpad, new port where assigned to 129 series (to be check for function)

 Different SSI channel is used so minor porting of code is necessary to apply to and never untouched code of 123 series can run as is on 129 family. Good maybe some conditional compile clause.

 123 series PA function and pinout

(3Vcc side J1, GND side J2)

1 SSI PA2 J2 Pin 10

2 SSI PA3 J2 Pin 9

3 SSI RX PA4  J2 Pin 8 

4 SSI TX PA5 J1 Pin 8

*************** Issue on board by R9 R10 Zero Ohm resistor ******************

 PD0 <->  PB6 connected by R9

 PD1 <->  PB7 connected by R10

 

129 Series:

 Connected EK-LM4c129XL

  BP2 has signal of port A selectable by jumper/ Zero Ohm resistor (not installed by luck choice)

 (+3Vcc side X6 Odd pin number, Gnd Side X7 even pin number)

 1 SSI PM6 on X7-20 Where PA2 was

 2 SSI PQ1 on x7-18 where PA3 was

 3 SSI PP3 on X7-16 where PA4 was

 4 SSI PP4 on X6-15 where PA5 was

(PA2 routable to X7-14 thru R20 get shorted to PQ3)

(PA3 routable to X7-12 thru R19 get shorted to PQ2)

(PA4,PA5 are in the internal row of X6 Pin 18,20)

 

 DK-LM4C129

  Booster pack has no assignment to Port A, reduced single row resemble MSP430 BP than Tiva

 (J6 3Vcc Side, J10 just provide extra gnd and +5Vcc, J9 ground side)

J6

1 SSI PH5 J6 Pin 10

2 SSI PP6 J6 Pin 9

3 SSI PD5 J6 Pin 8

4 SSI  PS6 J9 Pin 8

  • Hello Roberto,

    Thanks for starting. May I suggest a running document so all of us can contribute?

    Regards

    Amit

  • Amit Ashara said:
    Thanks for starting. May I suggest a running document so all of us can contribute?

     Amit my answer is forever yes, just take care next week start up exam session and my free time get low for a while, after that project setup get in force to start sooner, I can have more free space on August when I think a small vacation is in my need.

     I can just contribute to what I know, my project is a Huge multiplatform and I am not using all hardware of TIVA, biggest part is on an FPGA and not simply portable also if for every old HW part I wrote both VHDL and pure C software emulation and drivers. I got some confidence on ENET but I abandoned 1588 PTP in favour of dual CAN BUS timing. Slowly can be I completely grasp processor or may be not.