• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 30 subscribers
  • Views 3611 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Interrupt vector table alignment and thumb code

Vineel Kumar Reddy Kovvuri
Prodigy 80 points
Other Parts Discussed in Thread: TM4C123GH6PM

Hi All,

When I was going through the following paragraph in tm4c123gh6pm datasheet. I didn't quite understood why does the datasheet mentions the  The least-significant bit of each vector must be 1, indicating that the

exception handler is Thumb code.  The interrupt vector table have the address 0x0, 0x4, 0x8, 0xc etc....  Isn't it the most significant bit? Or Am I missing something here.

"Vector Table

The vector table contains the reset value of the stack pointer and the start addresses, also called
exception vectors, for all exception handlers. The vector table is constructed using the vector address
or offset shown in Table 2-8 on page 103. Figure 2-6 on page 107 shows the order of the exception
vectors in the vector table. The least-significant bit of each vector must be 1, indicating that the
exception handler is Thumb code"

Thanks

-Vineel

  • 0
    TI__Guru**** 244380 points

    Hello Vineet

    As per Cortex M architecture the address map of all entries other than SP (Stack Pointer) must be +1 of the actual address placement,

    As an example

    0x0 SP 0x20001000

    0x4 PC 0xE81

    In which case the first location for execution will be 0xE80. The +1 makes it Least significant bit as 1. For more details you can visit the ARM website

    Regards

    Amit

  • 0 in reply to Amit Ashara
    Prodigy 80 points

    Hi Amit,

    Are you referring to the below in the Cortex-M4 TRM?

    "3.9 Exceptions

    Vector table entries are compatible with interworking between ARM and Thumb instructions.This causes bit [0] of the vector value to load into the Execution Program Status Register (EPSR) T-bit on exception entry. All populated vectors in the vector table entries must have bit [0] set. Creating a table entry with bit [0] clear generates an INVSTATE fault on the first instruction of the handler corresponding to this vector."


    Thanks alot for the info. So because of the compatibility with interworking between ARM(32bit) and Thumb(16bit) code. The address that is stored in the vector table should have least significant bit set. Please correct me if I am wrong. I am under the wrong assumption that the vector offset itself should have bit[0] set. Thanks again.

  • 0 in reply to Vineel Kumar Reddy Kovvuri
    Guru 26105 points

    Hi,

    That's the correct answer. But, one mention to be taken into account: you do not need to write yourself the vector table with all items having the bit set to 1 -  this is automatically accomplished by the tools, provided that each item in the vector table is declared as "week". This is less obvious if you use CCS, since CCS knows about and make it for you. Other tools have special declarations and processed consequently.

    Petrei