TM4C1294 EPI GPIO Mode

Leethal

Hi,

I would like to try to use the EPI for 24 bit (3 Byte) GPIO reads. I haven't been able to find how to trigger the read from software for a single read although it is mentioned in the datasheet that the General Purpose mode has a general parallel type with which the rate of access can be controlled by software. (P847 bottom paragraph) It isn't evident to me how this is achieved. I am not using clocking or address data, just a 3 byte wide GPIO read that can be requested from a function triggered by a timer.

While I could use 3 separate GPIO ports to do this it is a little had to find 3 undedicated ports on the EK-TM4C1294 and the EPI pins are easily accessible.

Can someone clarify how/if this can be done.

over 10 years ago

0 Amit Ashara over 10 years ago

TI__Guru**** 244400 points

Hello Leethal,

The EPI pins are available on the bread board connector on the bottom. As to the access in general purpose mode, the Address Map has to be setup. Once the EPI Address Map is setup a read or write to the Address Map would trigger the external access to the pad.

Regards
Amit

0 Leethal over 10 years ago in reply to Amit Ashara

Intellectual 695 points

Hi Amit,

Sorry about the delay. Once I have mapped the address to say C000.0000 and have set the size to 24bits, would the read be as simple as
var = HWREG(0xC0000000 ); or do I need to read via an EPI register?

Regards,
Lee.

0 Amit Ashara over 10 years ago in reply to Leethal

TI__Guru**** 244400 points

Hello Lee,

It would be as simple as you mentioned.

Regards
Amit

0 Leethal over 10 years ago in reply to Amit Ashara

Intellectual 695 points

Hi Amit,

I have tried applying 3.3V to PH0 (signal 0) and doing a read with the following (taken from hello world). I was wondering if I am configuring it correctly? I have inserted the config file and the read is in the main while loop.

I should clarify that the variable EPI_Read remains 0 upon read.

int
main(void)
{

	volatile uint32_t EPI_Read = 0;
    //
    // Run from the PLL at 120 MHz.
    //
    g_ui32SysClock = MAP_SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ |
                SYSCTL_OSC_MAIN | SYSCTL_USE_PLL |
                SYSCTL_CFG_VCO_480), 120000000);

    //
    // Configure the device pins.
    //
    PinoutSet(false, false);
    //

    EPI_Config_GPIO();//Configure EPI

    //
    // Enable the GPIO pins for the LED D1 (PN1).
    //
    ROM_GPIOPinTypeGPIOOutput(GPIO_PORTN_BASE, GPIO_PIN_1);

    LEDWrite(CLP_D1, 0);//Turn Off LED


    //
    while(1)
    {

        //
        // Delay for a bit.
        //
        SysCtlDelay(g_ui32SysClock / 10 / 3);

    	EPI_Read = HWREG(EPI_PORT);

    	if((EPI_Read & 0x0F)== 0x00)//LED is off if Port (EPI_Read) is 0
    	{
    		LEDWrite(CLP_D1, 0);//Turn Off LED
    	}
    	else if ((EPI_Read & 0x0F) != 0x00)//just look at the bottom 4 bits for a change

    	{
    		LEDWrite(CLP_D1, 1);//Turn On LED
    	}//




    }
}

*******************************************************************************

#include "EPI_Config_GPIO.h"
#include <stdint.h>
#include <stdbool.h>
#include "inc/hw_memmap.h"
#include "driverlib/gpio.h"
#include "driverlib/pin_map.h"
#include "driverlib/rom.h"
#include "driverlib/rom_map.h"
#include "driverlib/sysctl.h"
#include "driverlib/epi.h"


//from  header file
#define EPI_PORT 0xA0000000
void EPI_Config_GPIO(void);



void EPI_Config_GPIO(void)
{
//Enable EPI
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_EPI0);
//Configure the EPI
EPIModeSet(EPI0_BASE,EPI_MODE_GENERAL);
EPIConfigGPModeSet(EPI0_BASE, EPI_GPMODE_ASIZE_NONE|EPI_GPMODE_DSIZE_24,0, 0);//No Clock out, No address, 24bit
EPIAddressMapSet(EPI0_BASE,EPI_ADDR_PER_BASE_A|EPI_ADDR_PER_BASE_NONE); //Address map to 0xA000.0000

//
// Enable Peripheral Clocks
//
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_EPI0);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOH);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOK);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOL);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOM);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPION);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOQ);

//
// Enable pin PH0 for EPI0 EPI0S0
//
MAP_GPIOPinConfigure(GPIO_PH0_EPI0S0);
//
// Enable pin PH1 for EPI0 EPI0S1
//
MAP_GPIOPinConfigure(GPIO_PH1_EPI0S1);
//
// Enable pin PH2 for EPI0 EPI0S2
//
MAP_GPIOPinConfigure(GPIO_PH2_EPI0S2);
//
// Enable pin PH3 for EPI0 EPI0S3
//
MAP_GPIOPinConfigure(GPIO_PH3_EPI0S3);
//
// Enable pin PC7 for EPI0 EPI0S4
//
MAP_GPIOPinConfigure(GPIO_PC7_EPI0S4);
//
// Enable pin PC6 for EPI0 EPI0S5
//
MAP_GPIOPinConfigure(GPIO_PC6_EPI0S5);
//
// Enable pin PC5 for EPI0 EPI0S6
//
MAP_GPIOPinConfigure(GPIO_PC5_EPI0S6);
//
// Enable pin PC4 for EPI0 EPI0S7
//
MAP_GPIOPinConfigure(GPIO_PC4_EPI0S7);
//
// Enable pin PA6 for EPI0 EPI0S8
//
MAP_GPIOPinConfigure(GPIO_PA6_EPI0S8);
//
// Enable pin PA7 for EPI0 EPI0S9
//
MAP_GPIOPinConfigure(GPIO_PA7_EPI0S9);
//
// Enable pin PG1 for EPI0 EPI0S10
//
MAP_GPIOPinConfigure(GPIO_PG1_EPI0S10);
//
// Enable pin PG0 for EPI0 EPI0S11
//
MAP_GPIOPinConfigure(GPIO_PG0_EPI0S11);
//
// Enable pin PM3 for EPI0 EPI0S12
//
MAP_GPIOPinConfigure(GPIO_PM3_EPI0S12);
//
// Enable pin PM2 for EPI0 EPI0S13
//
MAP_GPIOPinConfigure(GPIO_PM2_EPI0S13);
//
// Enable pin PM1 for EPI0 EPI0S14
//
MAP_GPIOPinConfigure(GPIO_PM1_EPI0S14);
//
// Enable pin PM0 for EPI0 EPI0S15
//
MAP_GPIOPinConfigure(GPIO_PM0_EPI0S15);
//
// Enable pin PL0 for EPI0 EPI0S16
//
MAP_GPIOPinConfigure(GPIO_PL0_EPI0S16);
//
// Enable pin PL1 for EPI0 EPI0S17
//
MAP_GPIOPinConfigure(GPIO_PL1_EPI0S17);
//
// Enable pin PL2 for EPI0 EPI0S18
//
MAP_GPIOPinConfigure(GPIO_PL2_EPI0S18);
//
// Enable pin PL3 for EPI0 EPI0S19
//
MAP_GPIOPinConfigure(GPIO_PL3_EPI0S19);
//
// Enable pin PQ0 for EPI0 EPI0S20
//
MAP_GPIOPinConfigure(GPIO_PQ0_EPI0S20);
//
// Enable pin PQ1 for EPI0 EPI0S21
//
MAP_GPIOPinConfigure(GPIO_PQ1_EPI0S21);
//
// Enable pin PQ2 for EPI0 EPI0S22
//
MAP_GPIOPinConfigure(GPIO_PQ2_EPI0S22);
//
// Enable pin PQ3 for EPI0 EPI0S23
//
MAP_GPIOPinConfigure(GPIO_PQ3_EPI0S23);
//
// Enable pin PK7 for EPI0 EPI0S24
//
//MAP_GPIOPinConfigure(GPIO_PK7_EPI0S24);
//GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_7);
//
// Enable pin PK6 for EPI0 EPI0S25
//
//MAP_GPIOPinConfigure(GPIO_PK6_EPI0S25);
//GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_6);
//
// Enable pin PL4 for EPI0 EPI0S26
//
//MAP_GPIOPinConfigure(GPIO_PL4_EPI0S26);
//GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_4);
//
// Enable pin PB2 for EPI0 EPI0S27
//
//MAP_GPIOPinConfigure(GPIO_PB2_EPI0S27);
//GPIOPinTypeEPI(GPIO_PORTB_BASE, GPIO_PIN_2);
//
// Enable pin PB3 for EPI0 EPI0S28
//
//MAP_GPIOPinConfigure(GPIO_PB3_EPI0S28);
//GPIOPinTypeEPI(GPIO_PORTB_BASE, GPIO_PIN_3);
//
// Enable pin PN2 for EPI0 EPI0S29
//
//MAP_GPIOPinConfigure(GPIO_PN2_EPI0S29);
//GPIOPinTypeEPI(GPIO_PORTN_BASE, GPIO_PIN_2);
//
// Enable pin PN3 for EPI0 EPI0S30
//
//MAP_GPIOPinConfigure(GPIO_PN3_EPI0S30);
//GPIOPinTypeEPI(GPIO_PORTN_BASE, GPIO_PIN_3);

//
// Enable pin PK5 for EPI0 EPI0S31
//
//MAP_GPIOPinConfigure(GPIO_PK5_EPI0S31);
//GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_5);
//
// Enable pin PK4 for EPI0 EPI0S32
//
//MAP_GPIOPinConfigure(GPIO_PK4_EPI0S32);
//GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_4);
//
// Enable pin PL5 for EPI0 EPI0S33
//
//MAP_GPIOPinConfigure(GPIO_PL5_EPI0S33);
//GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_5);
//
// Enable pin PN5 for EPI0 EPI0S35
//
//MAP_GPIOPinConfigure(GPIO_PN5_EPI0S35);
//GPIOPinTypeEPI(GPIO_PORTN_BASE, GPIO_PIN_5);
//
// Enable pin PN4 for EPI0 EPI0S34
//
//MAP_GPIOPinConfigure(GPIO_PN4_EPI0S34);
//GPIOPinTypeEPI(GPIO_PORTN_BASE, GPIO_PIN_4);


GPIODirModeSet(GPIO_PORTH_BASE,GPIO_PIN_3|GPIO_PIN_2|GPIO_PIN_1|GPIO_PIN_0, GPIO_DIR_MODE_IN);
GPIOPadConfigSet(GPIO_PORTH_BASE,GPIO_PIN_3|GPIO_PIN_2|GPIO_PIN_1|GPIO_PIN_0, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
GPIODirModeSet(GPIO_PORTC_BASE,GPIO_PIN_7|GPIO_PIN_6|GPIO_PIN_5|GPIO_PIN_4, GPIO_DIR_MODE_IN);
GPIOPadConfigSet(GPIO_PORTC_BASE,GPIO_PIN_7|GPIO_PIN_6|GPIO_PIN_5|GPIO_PIN_4, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
GPIODirModeSet(GPIO_PORTA_BASE,GPIO_PIN_7|GPIO_PIN_6, GPIO_DIR_MODE_IN);
GPIOPadConfigSet(GPIO_PORTA_BASE,GPIO_PIN_7|GPIO_PIN_6, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
GPIODirModeSet(GPIO_PORTG_BASE,GPIO_PIN_1|GPIO_PIN_0, GPIO_DIR_MODE_IN);
GPIOPadConfigSet(GPIO_PORTG_BASE,GPIO_PIN_1|GPIO_PIN_0, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
GPIODirModeSet(GPIO_PORTM_BASE,GPIO_PIN_3|GPIO_PIN_2|GPIO_PIN_1|GPIO_PIN_0, GPIO_DIR_MODE_IN);
GPIOPadConfigSet(GPIO_PORTM_BASE,GPIO_PIN_3|GPIO_PIN_2|GPIO_PIN_1|GPIO_PIN_0, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
GPIODirModeSet(GPIO_PORTL_BASE,GPIO_PIN_3|GPIO_PIN_2|GPIO_PIN_1|GPIO_PIN_0, GPIO_DIR_MODE_IN);
GPIOPadConfigSet(GPIO_PORTL_BASE,GPIO_PIN_3|GPIO_PIN_2|GPIO_PIN_1|GPIO_PIN_0, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
GPIODirModeSet(GPIO_PORTQ_BASE,GPIO_PIN_3|GPIO_PIN_2|GPIO_PIN_1|GPIO_PIN_0, GPIO_DIR_MODE_IN);
GPIOPadConfigSet(GPIO_PORTQ_BASE,GPIO_PIN_3|GPIO_PIN_2|GPIO_PIN_1|GPIO_PIN_0, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);

}

0 Amit Ashara over 10 years ago in reply to Leethal

TI__Guru**** 244400 points

Hello Leethal,

The following section of code is the problem. When you have set the Base Address the size of None should be changed to the size of the Address space.

EPIAddressMapSet(EPI0_BASE,EPI_ADDR_PER_BASE_A|EPI_ADDR_PER_BASE_NONE); //Address map to 0xA000.0000

Regards
Amit

0 Leethal over 10 years ago in reply to Amit Ashara

Intellectual 695 points

Hi Amit,

It could be that I'm not understanding here but,

The define: #define EPI_GPMODE_ASIZE_NONE 0x00000000

and the following from page 821 of the manual section 7:

program the EPADR field to 0x1 for address 0xA000.0000 or 0x2 for address 0xC000.0000; and program the EPSZ field to 0x0 for 256 bytes

seem to suggest the EPSZ field should be set to 0x00 which should give a size of 256 bytes.

Is this incorrect??

Regards,
Lee.

0 Amit Ashara over 10 years ago in reply to Leethal

TI__Guru**** 244400 points

Hello Lee,

Just to double check, please send the value of the EPIADDRMAP register after EPI is programmed.

Also I found one more issue with the code. You are using

GPIODirModeSet(GPIO_PORTH_BASE,GPIO_PIN_3|GPIO_PIN_2|GPIO_PIN_1|GPIO_PIN_0, GPIO_DIR_MODE_IN);
GPIOPadConfigSet(GPIO_PORTH_BASE,GPIO_PIN_3|GPIO_PIN_2|GPIO_PIN_1|GPIO_PIN_0, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);

This will configure the GPIO as GPIO input mode and not peripheral controlled. Why in the first place did you remove GPIOPinTypeEPI(GPIO_PORTN_BASE, GPIO_PIN_4);

which is the correct API to use.

Regards
Amit

0 Leethal over 10 years ago in reply to Amit Ashara

Intellectual 695 points

Hi Amit,

Just grabbed the value.

EPI_ADDRMAP 0x00000010 EPI Address Map [Memory Mapped]

I did change various things in an attempt to get an output . Also worth noting that the PinMux utility produces a MAP_GPIOPinTypeEPI() which doesn't seem to exist although GPIOPinTypeEPI() does.

Regards,
Lee.

0 Amit Ashara over 10 years ago in reply to Leethal

TI__Guru**** 244400 points

Hello Lee,

Then can you replace the MAP_GPIOPinTypeEPI with GPIOPinTypeEPI. Also do include the gpio.h and pin_map.h in driverlib.

Regards
Amit

0 Leethal over 10 years ago in reply to Amit Ashara

Intellectual 695 points

Hi Amit,

They are included and I have just managed to read the port. However this was only on the first iteration. The variable EPI_Read seems to maintain the value of the first read (1) and doesn't update on further iterations should I remove the applied voltage or move it to another pin. Is this possibly normal behavior as it has 256 bytes for size?

I include the current configuration file

#include "EPI_Config_GPIO.h"
#include <stdint.h>
#include <stdbool.h>
#include "inc/hw_memmap.h"
#include "inc/hw_types.h"
#include "driverlib/gpio.h"
#include "driverlib/pin_map.h"
#include "driverlib/rom.h"
#include "driverlib/rom_map.h"
#include "driverlib/sysctl.h"
#include "driverlib/epi.h"
#include "inc/hw_epi.h"








void EPI_Config_GPIO(void)
{
	//
	// Enable pin PH0 for EPI0 EPI0S0
	//
	MAP_GPIOPinConfigure(GPIO_PH0_EPI0S0);
	GPIOPinTypeEPI(GPIO_PORTH_BASE, GPIO_PIN_0);
	//
	// Enable pin PH1 for EPI0 EPI0S1
	//
	MAP_GPIOPinConfigure(GPIO_PH1_EPI0S1);
	GPIOPinTypeEPI(GPIO_PORTH_BASE, GPIO_PIN_1);
	//
	// Enable pin PH2 for EPI0 EPI0S2
	//
	MAP_GPIOPinConfigure(GPIO_PH2_EPI0S2);
	GPIOPinTypeEPI(GPIO_PORTH_BASE, GPIO_PIN_2);
	//
	// Enable pin PH3 for EPI0 EPI0S3
	//
	MAP_GPIOPinConfigure(GPIO_PH3_EPI0S3);
	GPIOPinTypeEPI(GPIO_PORTH_BASE, GPIO_PIN_3);
	//
	// Enable pin PC7 for EPI0 EPI0S4
	//
	MAP_GPIOPinConfigure(GPIO_PC7_EPI0S4);
	GPIOPinTypeEPI(GPIO_PORTC_BASE, GPIO_PIN_7);
	//
	// Enable pin PC6 for EPI0 EPI0S5
	//
	MAP_GPIOPinConfigure(GPIO_PC6_EPI0S5);
	GPIOPinTypeEPI(GPIO_PORTC_BASE, GPIO_PIN_6);
	//
	// Enable pin PC5 for EPI0 EPI0S6
	//
	MAP_GPIOPinConfigure(GPIO_PC5_EPI0S6);
	//GPIOPinTypeEPI(GPIO_PORTC_BASE, GPIO_PIN_5);
	//
	// Enable pin PC4 for EPI0 EPI0S7
	//
	MAP_GPIOPinConfigure(GPIO_PC4_EPI0S7);
	GPIOPinTypeEPI(GPIO_PORTC_BASE, GPIO_PIN_4);
	//
	// Enable pin PA6 for EPI0 EPI0S8
	//
	MAP_GPIOPinConfigure(GPIO_PA6_EPI0S8);
	GPIOPinTypeEPI(GPIO_PORTA_BASE, GPIO_PIN_6);
	//
	// Enable pin PA7 for EPI0 EPI0S9
	//
	MAP_GPIOPinConfigure(GPIO_PA7_EPI0S9);
	GPIOPinTypeEPI(GPIO_PORTA_BASE, GPIO_PIN_7);
	//
	// Enable pin PG1 for EPI0 EPI0S10
	//
	MAP_GPIOPinConfigure(GPIO_PG1_EPI0S10);
	GPIOPinTypeEPI(GPIO_PORTG_BASE, GPIO_PIN_1);
	//
	// Enable pin PG0 for EPI0 EPI0S11
	//
	MAP_GPIOPinConfigure(GPIO_PG0_EPI0S11);
	GPIOPinTypeEPI(GPIO_PORTG_BASE, GPIO_PIN_0);
	//
	// Enable pin PM3 for EPI0 EPI0S12
	//
	MAP_GPIOPinConfigure(GPIO_PM3_EPI0S12);
	GPIOPinTypeEPI(GPIO_PORTM_BASE, GPIO_PIN_3);
	//
	// Enable pin PM2 for EPI0 EPI0S13
	//
	MAP_GPIOPinConfigure(GPIO_PM2_EPI0S13);
	GPIOPinTypeEPI(GPIO_PORTM_BASE, GPIO_PIN_2);
	//
	// Enable pin PM1 for EPI0 EPI0S14
	//
	MAP_GPIOPinConfigure(GPIO_PM1_EPI0S14);
	GPIOPinTypeEPI(GPIO_PORTM_BASE, GPIO_PIN_1);
	//
	// Enable pin PM0 for EPI0 EPI0S15
	//
	MAP_GPIOPinConfigure(GPIO_PM0_EPI0S15);
	GPIOPinTypeEPI(GPIO_PORTM_BASE, GPIO_PIN_0);
	//
	// Enable pin PL0 for EPI0 EPI0S16
	//
	MAP_GPIOPinConfigure(GPIO_PL0_EPI0S16);
	GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_0);
	//
	// Enable pin PL1 for EPI0 EPI0S17
	//
	MAP_GPIOPinConfigure(GPIO_PL1_EPI0S17);
	GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_1);
	//
	// Enable pin PL2 for EPI0 EPI0S18
	//
	MAP_GPIOPinConfigure(GPIO_PL2_EPI0S18);
	GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_2);
	//
	// Enable pin PL3 for EPI0 EPI0S19
	//
	MAP_GPIOPinConfigure(GPIO_PL3_EPI0S19);
	GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_3);
	//
	// Enable pin PQ0 for EPI0 EPI0S20
	//
	MAP_GPIOPinConfigure(GPIO_PQ0_EPI0S20);
	GPIOPinTypeEPI(GPIO_PORTQ_BASE, GPIO_PIN_0);
	//
	// Enable pin PQ1 for EPI0 EPI0S21
	//
	MAP_GPIOPinConfigure(GPIO_PQ1_EPI0S21);
	GPIOPinTypeEPI(GPIO_PORTQ_BASE, GPIO_PIN_1);
	//
	// Enable pin PQ2 for EPI0 EPI0S22
	//
	MAP_GPIOPinConfigure(GPIO_PQ2_EPI0S22);
	GPIOPinTypeEPI(GPIO_PORTQ_BASE, GPIO_PIN_2);
	//
	// Enable pin PQ3 for EPI0 EPI0S23
	//
	MAP_GPIOPinConfigure(GPIO_PQ3_EPI0S23);
	GPIOPinTypeEPI(GPIO_PORTQ_BASE, GPIO_PIN_3);
	//
	// Enable pin PK7 for EPI0 EPI0S24
	//
	//MAP_GPIOPinConfigure(GPIO_PK7_EPI0S24);
	//GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_7);
	//
	// Enable pin PK6 for EPI0 EPI0S25
	//
	//MAP_GPIOPinConfigure(GPIO_PK6_EPI0S25);
	//GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_6);
	//
	// Enable pin PL4 for EPI0 EPI0S26
	//
	//MAP_GPIOPinConfigure(GPIO_PL4_EPI0S26);
	//GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_4);
	//
	// Enable pin PB2 for EPI0 EPI0S27
	//
	//MAP_GPIOPinConfigure(GPIO_PB2_EPI0S27);
	//GPIOPinTypeEPI(GPIO_PORTB_BASE, GPIO_PIN_2);
	//
	// Enable pin PB3 for EPI0 EPI0S28
	//
	//MAP_GPIOPinConfigure(GPIO_PB3_EPI0S28);
	//GPIOPinTypeEPI(GPIO_PORTB_BASE, GPIO_PIN_3);
	//
	// Enable pin PN2 for EPI0 EPI0S29
	//
	//MAP_GPIOPinConfigure(GPIO_PN2_EPI0S29);
	//GPIOPinTypeEPI(GPIO_PORTN_BASE, GPIO_PIN_2);
	//
	// Enable pin PN3 for EPI0 EPI0S30
	//
	//MAP_GPIOPinConfigure(GPIO_PN3_EPI0S30);
	//GPIOPinTypeEPI(GPIO_PORTN_BASE, GPIO_PIN_3);

	//
	// Enable pin PK5 for EPI0 EPI0S31
	//
	//MAP_GPIOPinConfigure(GPIO_PK5_EPI0S31);
	//GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_5);
	//
	// Enable pin PK4 for EPI0 EPI0S32
	//
	//MAP_GPIOPinConfigure(GPIO_PK4_EPI0S32);
	//GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_4);
	//
	// Enable pin PL5 for EPI0 EPI0S33
	//
	//MAP_GPIOPinConfigure(GPIO_PL5_EPI0S33);
	//GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_5);
	//
	// Enable pin PN5 for EPI0 EPI0S35
	//
	//MAP_GPIOPinConfigure(GPIO_PN5_EPI0S35);
	//GPIOPinTypeEPI(GPIO_PORTN_BASE, GPIO_PIN_5);
	//
	// Enable pin PN4 for EPI0 EPI0S34
	//
	//MAP_GPIOPinConfigure(GPIO_PN4_EPI0S34);
	//GPIOPinTypeEPI(GPIO_PORTN_BASE, GPIO_PIN_4);


	// Enable Peripheral Clock
	//
	MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_EPI0);//Enable EPI
	//Configure the EPI
	EPIModeSet(EPI0_BASE,EPI_MODE_GENERAL);
	EPIDividerSet(EPI0_BASE,1);// check whether required.
	EPIConfigGPModeSet(EPI0_BASE, EPI_GPMODE_ASIZE_NONE|EPI_GPMODE_DSIZE_24,0, 0);//No Clock out, No address, 24bit
	EPIAddressMapSet(EPI0_BASE,EPI_ADDR_PER_BASE_A|EPI_ADDR_PER_BASE_NONE); //Address map to 0xA000.0000
	// Wait for the EPI initialization to complete.
	//
	while(HWREG(EPI0_BASE + EPI_O_STAT) & EPI_STAT_INITSEQ)
	{
		//
		// Wait for initialization to complete.
		//
	}
	//



}

Thank you for your assistance so far. It is possible that further configuration is required or that I must use the EPI Registers for Non Blocking reads for this to function correctly?

0 Amit Ashara over 10 years ago in reply to Leethal

TI__Guru**** 244400 points

Hello Leethal,

First of all the while loop is needed for SDRAM mode. Secondly, the address space is mapped for 256 bytes so only if you increment the address does the location change require. The Data path must not be affected by the address.

As long as the voltage is applied the data shall always read 1. Remember that the CPU and EPI is working faster than the voltage application and removal. It would be good to make the change to another pin and Pull Down applied via the GPIOPDR register to provide for a discharge path.

Regards
Amit

0 Leethal over 10 years ago in reply to Amit Ashara

Intellectual 695 points

Hi Amit,

I have the read in the while loop for testing only at the moment. The data will eventualy be sent as bytes to the Ethernet (LWIP) stack. (This part is functioning :)) My initial test was to turn on or off the LED when I applied or removed the voltage on the pin running in the while loop. As this didn't work I tried a few variations such as trying to reset the previously read value with a deferenced pointer as an lvalue such as HREG[EPI_Port] = 0; while stepping with the debugger. The value at the EPI address always remained whatever was read first.

Perhaps I don't quite understand the hardware and require a pull down as you suggest. I am as always grateful for you help.

Regards,

Lee.

0 Leethal over 10 years ago in reply to Leethal

Intellectual 695 points

Hi again Amit,

I have tried the weak pull down as suggested but there is no change to the value read from the memory location after the first read despite trying applying and removing the 3.3V from different pins of the bottom 4 pins of the EPI. I have added the pin set just before main{}.

I'm obviously overlooking something however applying a GND to the pin that was initially set to 1 by 3.3V on the pin doesn't affect the value read by

var = HREG [ EPI_PORT]. Also applying 3.3V to another pin doesn't change the value read???

// Copyright (c) 2013-2014 Texas Instruments Incorporated.  All rights reserved.
// Software License Agreement
// 
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
// 
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
// 
// This is part of revision 2.1.0.12573 of the EK-TM4C1294XL Firmware Package.
//
//*****************************************************************************

#include <stdint.h>
#include <stdbool.h>
#include "inc/hw_memmap.h"
#include "inc/hw_types.h"
#include "driverlib/gpio.h"
#include "drivers/pinout.h"
#include "driverlib/pin_map.h"
#include "driverlib/rom.h"
#include "driverlib/rom_map.h"
#include "driverlib/sysctl.h"
#include "driverlib/uart.h"
#include "utils/uartstdio.h"
#include "EPI_Config_GPIO.h"
#include "driverlib/epi.h"



//*****************************************************************************
//
//! \addtogroup example_list
//! <h1>Hello World (hello)</h1>
//!
//! A very simple ``hello world'' example.  It simply displays ``Hello World!''
//! on the UART and is a starting point for more complicated applications.
//!
//! Open a terminal with 115,200 8-N-1 to see the output for this demo.
//
//*****************************************************************************

//*****************************************************************************
//
// System clock rate in Hz.
//
//*****************************************************************************
uint32_t g_ui32SysClock;

//*****************************************************************************
//
// The error routine that is called if the driver library encounters an error.
//
//*****************************************************************************
#ifdef DEBUG
void
__error__(char *pcFilename, uint32_t ui32Line)
{
}
#endif

//*****************************************************************************
//
// Configure the UART and its pins.  This must be called before UARTprintf().
//
//*****************************************************************************
//void
//ConfigureUART(void)
//{
    //
    // Enable the GPIO Peripheral used by the UART.
    //
//    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);

    //
    // Enable UART0
    //
 //   ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);

    //
    // Configure GPIO Pins for UART mode.
    //
  //  ROM_GPIOPinConfigure(GPIO_PA0_U0RX);
 //   ROM_GPIOPinConfigure(GPIO_PA1_U0TX);
 //   ROM_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);

    //
    // Initialize the UART for console I/O.
    //
  //  UARTStdioConfig(0, 115200, g_ui32SysClock);


//}

//*****************************************************************************
//
// Print "Hello World!" to the UART on the Intelligent UART Module.
//
//*****************************************************************************
int
main(void)
{

	volatile uint32_t EPI_Read = 0;


    // Run from the PLL at 120 MHz.
    //
    g_ui32SysClock = MAP_SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ |
                SYSCTL_OSC_MAIN | SYSCTL_USE_PLL |
                SYSCTL_CFG_VCO_480), 120000000);

    //
    // Configure the device pins.
    //
    PinoutSet(false, false);
    //

    EPI_Config_GPIO();//Configure EPI

    //
    // Enable the GPIO pins for the LED D1 (PN1).
    //
    ROM_GPIOPinTypeGPIOOutput(GPIO_PORTN_BASE, GPIO_PIN_1);

    LEDWrite(CLP_D1, 0);//Turn Off LED

    GPIOPadConfigSet(GPIO_PORTH_BASE,GPIO_PIN_3|GPIO_PIN_2|GPIO_PIN_1|GPIO_PIN_0,GPIO_STRENGTH_8MA,GPIO_PIN_TYPE_STD_WPD);

    //
    while(1)
    {

        //
        // Delay for a bit.
        //

    	SysCtlDelay(g_ui32SysClock / 10 / 3);

    	EPI_Read = HWREG(EPI_PORT);



    	if((EPI_Read & 0x0F)== 0x00)//LED is off if Port (EPI_Read) is 0
    	{
    		LEDWrite(CLP_D1, 0);//Turn Off LED
    	}
    	else if ((EPI_Read & 0x0F) != 0x00)//just look at the bottom 4 bits for a change

    	{
    		LEDWrite(CLP_D1, 1);//Turn On LED
    	}//




    }
}

Regards,

Lee.

0 Amit Ashara over 10 years ago in reply to Leethal

TI__Guru**** 244400 points

Hello Lee,

OK, let me take the code and test to see what is going on.

Regards
Amit

0 Leethal over 10 years ago in reply to Amit Ashara

Intellectual 695 points

Thanks Amit. I do hope you can get it working. It seems the most effective way to get at 3 (8 bit) ports. on that board. In the meantime I'm going to create a TI-RTOS version of the project.

Regards,

Lee.

0 Amit Ashara over 10 years ago in reply to Leethal

TI__Guru**** 244400 points

Hello Lee,

I think this was there in the forum and I took the code for GP Mode. The CLKPIN function has to be enabled (clock may still not be required at the IO to toggle)

EPIConfigGPModeSet(EPI0_BASE, EPI_GPMODE_CLKPIN|EPI_GPMODE_ASIZE_NONE|EPI_GPMODE_DSIZE_24,0, 0);//No Clock out, No address, 24bit

Regards
Amit

0 Leethal over 10 years ago in reply to Amit Ashara

Intellectual 695 points

Hi Amit,

Thank you for your support. I really appreciate it. EPI GP mode is now happily functioning.

I'll leave the config file here in case someone else needs it and can't find or overlooks the details.

//#include "EPI_Config_GPIO.h"
#include <stdint.h>
#include <stdbool.h>
#include "inc/hw_memmap.h"
#include "inc/hw_types.h"
#include "driverlib/gpio.h"
#include "driverlib/pin_map.h"
#include "driverlib/rom.h"
#include "driverlib/rom_map.h"
#include "driverlib/sysctl.h"
#include "driverlib/epi.h"
#include "inc/hw_epi.h"

#define EPI_PORT 0xA0000000

//from header

void EPI_Config_GPIO(void);

//from header




void EPI_Config_GPIO(void)
{
	//
	// Enable pin PH0 for EPI0 EPI0S0
	//
	MAP_GPIOPinConfigure(GPIO_PH0_EPI0S0);
	GPIOPinTypeEPI(GPIO_PORTH_BASE, GPIO_PIN_0);
	//
	// Enable pin PH1 for EPI0 EPI0S1
	//
	MAP_GPIOPinConfigure(GPIO_PH1_EPI0S1);
	GPIOPinTypeEPI(GPIO_PORTH_BASE, GPIO_PIN_1);
	//
	// Enable pin PH2 for EPI0 EPI0S2
	//
	MAP_GPIOPinConfigure(GPIO_PH2_EPI0S2);
	GPIOPinTypeEPI(GPIO_PORTH_BASE, GPIO_PIN_2);
	//
	// Enable pin PH3 for EPI0 EPI0S3
	//
	MAP_GPIOPinConfigure(GPIO_PH3_EPI0S3);
	GPIOPinTypeEPI(GPIO_PORTH_BASE, GPIO_PIN_3);
	//
	// Enable pin PC7 for EPI0 EPI0S4
	//
	MAP_GPIOPinConfigure(GPIO_PC7_EPI0S4);
	GPIOPinTypeEPI(GPIO_PORTC_BASE, GPIO_PIN_7);
	//
	// Enable pin PC6 for EPI0 EPI0S5
	//
	MAP_GPIOPinConfigure(GPIO_PC6_EPI0S5);
	GPIOPinTypeEPI(GPIO_PORTC_BASE, GPIO_PIN_6);
	//
	// Enable pin PC5 for EPI0 EPI0S6
	//
	MAP_GPIOPinConfigure(GPIO_PC5_EPI0S6);
	//GPIOPinTypeEPI(GPIO_PORTC_BASE, GPIO_PIN_5);
	//
	// Enable pin PC4 for EPI0 EPI0S7
	//
	MAP_GPIOPinConfigure(GPIO_PC4_EPI0S7);
	GPIOPinTypeEPI(GPIO_PORTC_BASE, GPIO_PIN_4);
	//
	// Enable pin PA6 for EPI0 EPI0S8
	//
	MAP_GPIOPinConfigure(GPIO_PA6_EPI0S8);
	GPIOPinTypeEPI(GPIO_PORTA_BASE, GPIO_PIN_6);
	//
	// Enable pin PA7 for EPI0 EPI0S9
	//
	MAP_GPIOPinConfigure(GPIO_PA7_EPI0S9);
	GPIOPinTypeEPI(GPIO_PORTA_BASE, GPIO_PIN_7);
	//
	// Enable pin PG1 for EPI0 EPI0S10
	//
	MAP_GPIOPinConfigure(GPIO_PG1_EPI0S10);
	GPIOPinTypeEPI(GPIO_PORTG_BASE, GPIO_PIN_1);
	//
	// Enable pin PG0 for EPI0 EPI0S11
	//
	MAP_GPIOPinConfigure(GPIO_PG0_EPI0S11);
	GPIOPinTypeEPI(GPIO_PORTG_BASE, GPIO_PIN_0);
	//
	// Enable pin PM3 for EPI0 EPI0S12
	//
	MAP_GPIOPinConfigure(GPIO_PM3_EPI0S12);
	GPIOPinTypeEPI(GPIO_PORTM_BASE, GPIO_PIN_3);
	//
	// Enable pin PM2 for EPI0 EPI0S13
	//
	MAP_GPIOPinConfigure(GPIO_PM2_EPI0S13);
	GPIOPinTypeEPI(GPIO_PORTM_BASE, GPIO_PIN_2);
	//
	// Enable pin PM1 for EPI0 EPI0S14
	//
	MAP_GPIOPinConfigure(GPIO_PM1_EPI0S14);
	GPIOPinTypeEPI(GPIO_PORTM_BASE, GPIO_PIN_1);
	//
	// Enable pin PM0 for EPI0 EPI0S15
	//
	MAP_GPIOPinConfigure(GPIO_PM0_EPI0S15);
	GPIOPinTypeEPI(GPIO_PORTM_BASE, GPIO_PIN_0);
	//
	// Enable pin PL0 for EPI0 EPI0S16
	//
	MAP_GPIOPinConfigure(GPIO_PL0_EPI0S16);
	GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_0);
	//
	// Enable pin PL1 for EPI0 EPI0S17
	//
	MAP_GPIOPinConfigure(GPIO_PL1_EPI0S17);
	GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_1);
	//
	// Enable pin PL2 for EPI0 EPI0S18
	//
	MAP_GPIOPinConfigure(GPIO_PL2_EPI0S18);
	GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_2);
	//
	// Enable pin PL3 for EPI0 EPI0S19
	//
	MAP_GPIOPinConfigure(GPIO_PL3_EPI0S19);
	GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_3);
	//
	// Enable pin PQ0 for EPI0 EPI0S20
	//
	MAP_GPIOPinConfigure(GPIO_PQ0_EPI0S20);
	GPIOPinTypeEPI(GPIO_PORTQ_BASE, GPIO_PIN_0);
	//
	// Enable pin PQ1 for EPI0 EPI0S21
	//
	MAP_GPIOPinConfigure(GPIO_PQ1_EPI0S21);
	GPIOPinTypeEPI(GPIO_PORTQ_BASE, GPIO_PIN_1);
	//
	// Enable pin PQ2 for EPI0 EPI0S22
	//
	MAP_GPIOPinConfigure(GPIO_PQ2_EPI0S22);
	GPIOPinTypeEPI(GPIO_PORTQ_BASE, GPIO_PIN_2);
	//
	// Enable pin PQ3 for EPI0 EPI0S23
	//
	MAP_GPIOPinConfigure(GPIO_PQ3_EPI0S23);
	GPIOPinTypeEPI(GPIO_PORTQ_BASE, GPIO_PIN_3);
	//
	// Enable pin PK7 for EPI0 EPI0S24
	//
	//MAP_GPIOPinConfigure(GPIO_PK7_EPI0S24);
	//GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_7);
	//
	// Enable pin PK6 for EPI0 EPI0S25
	//
	//MAP_GPIOPinConfigure(GPIO_PK6_EPI0S25);
	//GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_6);
	//
	// Enable pin PL4 for EPI0 EPI0S26
	//
	//MAP_GPIOPinConfigure(GPIO_PL4_EPI0S26);
	//GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_4);
	//
	// Enable pin PB2 for EPI0 EPI0S27
	//
	//MAP_GPIOPinConfigure(GPIO_PB2_EPI0S27);
	//GPIOPinTypeEPI(GPIO_PORTB_BASE, GPIO_PIN_2);
	//
	// Enable pin PB3 for EPI0 EPI0S28
	//
	//MAP_GPIOPinConfigure(GPIO_PB3_EPI0S28);
	//GPIOPinTypeEPI(GPIO_PORTB_BASE, GPIO_PIN_3);
	//
	// Enable pin PN2 for EPI0 EPI0S29
	//
	//MAP_GPIOPinConfigure(GPIO_PN2_EPI0S29);
	//GPIOPinTypeEPI(GPIO_PORTN_BASE, GPIO_PIN_2);
	//
	// Enable pin PN3 for EPI0 EPI0S30
	//
	//MAP_GPIOPinConfigure(GPIO_PN3_EPI0S30);
	//GPIOPinTypeEPI(GPIO_PORTN_BASE, GPIO_PIN_3);

	//
	// Enable pin PK5 for EPI0 EPI0S31
	//
	//MAP_GPIOPinConfigure(GPIO_PK5_EPI0S31);
	//GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_5);
	//
	// Enable pin PK4 for EPI0 EPI0S32
	//
	//MAP_GPIOPinConfigure(GPIO_PK4_EPI0S32);
	//GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_4);
	//
	// Enable pin PL5 for EPI0 EPI0S33
	//
	//MAP_GPIOPinConfigure(GPIO_PL5_EPI0S33);
	//GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_5);
	//
	// Enable pin PN5 for EPI0 EPI0S35
	//
	//MAP_GPIOPinConfigure(GPIO_PN5_EPI0S35);
	//GPIOPinTypeEPI(GPIO_PORTN_BASE, GPIO_PIN_5);
	//
	// Enable pin PN4 for EPI0 EPI0S34
	//
	//MAP_GPIOPinConfigure(GPIO_PN4_EPI0S34);
	//GPIOPinTypeEPI(GPIO_PORTN_BASE, GPIO_PIN_4);


	// Enable Peripheral Clock
	//
	MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_EPI0);//Enable EPI
	//Configure the EPI
	EPIModeSet(EPI0_BASE,EPI_MODE_GENERAL);
	EPIDividerSet(EPI0_BASE,1);// check whether required.
	EPIConfigGPModeSet(EPI0_BASE, EPI_GPMODE_CLKPIN|EPI_GPMODE_ASIZE_NONE|EPI_GPMODE_DSIZE_24,0, 0);//No Clock out, No address, 24bit
	EPIAddressMapSet(EPI0_BASE,EPI_ADDR_PER_BASE_A|EPI_ADDR_PER_BASE_NONE);  //Address map to 0xA000.0000


}

Kind regards,

Lee.

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TM4C1294 EPI GPIO Mode