SYSCTL#16, Separate regulator for Analog & digital supply

Vindhyachal Takniki said:

Has anyone experience using separate regulators for Vdda & vddd?

Several years past - w/vendor's (now withdrawn) LX4F - we did exactly that!   And we noted & logged results.   Much like you - we sought to (avoid) the size/cost penalty of a separate, regulated supply.

Now prior to connecting to our "LX4F" MCU (vendor has stated, multiple times, that this is equivalent to TM4C123) we carefully measured the rise (and fall) times of each supply - and tried our best to "match" them.   Usually we found VDD to draw more current than VDDA - thus it would rise more slowly unless we compensated with filters/networks @ the MCU pins.  (especially the larger value of caps)

Our findings - which have worked for beyond 5K such MCUs in the field - a single 3V3 regulated supply (adequate to task) and which passed thru ferrite bead to VDDA, and had (high and low value) caps to ground - placed as close as possible to VDDA - much improved our MCU's ADC and has (thus far) not caused, "Life Issues."

Of course you are fully and solely responsible for your design.    (read the "provider of content" boiler-plate, base of this forum)  You've requested "experience" - I've so reported - bon chance mon ami...

Hi Amit,

Thanks, I will try by separate analog & digital supply.

Hello VT,

Both VDD and VDDA are analog supply. The digital is derived from VDD supply rail.

On a side note, the in rush is at LDO start up, so the VDDA need not be separate from the VDD LDO as the device is not functional at the beginning of the start up sequence. Also by using stepped operating frequency change and L and C on the VDDA ramp, the in rush affect can be minimized.

Regards
Amit

Amit Ashara said:

by using stepped operating frequency change

To be even clearer - by making each step smaller (i.e. more of them) - rather than larger (i.e. fewer steps) the in-rush current is better dampened...

Let's see if I have this correct. If I delay engaging the PLL for say 1s, simply running at the crystal frequency until then, then the ldo will have time to stabilize and any startup glitch will be minimized?

It does make a certain amount of sense

Robert

Hello cb1,

Yes, that is correct. The Bulk of the in-rush current is during the time when the LDO starts up from 0V to 1.2V. Subsequent changes to the operating conditions do create small in rush peak, but compared to the start up peak, this is way lesser.

Regards
Amit

Agreed there's (more) sense here than observed w/"unmarked/badly described" Rev challenged, MCUs.

My take, Robert - to play it (really) safe - (even w/your "delayed" PLL engagement) - do "not" jump from xtal freq. to "final" freq. in "one go."   As you/I often note & advise - the use of experimentation to harvest data - often provides needed insight.   Perhaps 1 or 2 "intermediate" frequency hops - prior to "full speed ahead" - may hold LDO to spec...

Hi Amit,

Attached I have made a basic circuit for TM4C123GH6PM. It has separate regulator for analog & digital supply.
Took reference from SPMA059 while designing for lower power operation. All caps/res used are of 0805 size.

1. Pins HIB & XOSC1 are left unconnected, since I am not using them.
2. Pins WAKE,GNDX,XOSC0: Grounded
3. SWD: SWCLK pulled low by 10K
SWDIO,TDI,SWO pulled up by 10K
Reset, pull up 10K & decouple 0.01uF
4.AVDD/AVSS: Decoupled by 1uF & 0.01uF.
5.DVDD/DVSS: Each set is decoupled by 0.1uF. & One has additional 0.01uF & 4.7uF
6. Vddc: One has decoupled by 2.2uF,1uF,0.1uF. & other is decoupled by 0.1uF
7. Vbat: Although I have to connect it to DVDD. I have used 51ohm & 0.1uF.
8. MOSC: MOSC & caps are used as same as in launchpad kit, except caps are of 0805 size.

Now in final circuit, some of pins will be NC. Earlier in one of thread you had suggested to use pull-down on unused pins.
1. What should be recommended value for pull-down resistor as MCU has latch up issue.However datasheet of MCU says to ground them.
2. Also placing one pull-down for each unused pin, will add to BOM. Can I short 4-5 pin together & then pull it down.If yes, however some of pins like PA0-1,PA2-5,PB2-3,PD7,PD7 & PF0 wake up as alternate function. I think shorting them with other pins may cause issue or I have to use separate pull-down resistor for each pin?

breakout.pdf

Hello VT,

While most of the connections seem right, I am not sure on SWCLK. Should it be a pull up or a pull down. I have seen pull ups only.
Having pull down on the unused pins gives the flexibility to connect them later. Having them to GND does not.

Regards
Amit

Hi Amit,

1. I took reference from here: www.support.code-red-tech.com/.../HardwareDebugConnections
Although its for NXP, but I think since it belong to M3 core, so might be same can be applied.

2. Since I dont need them in the circuit, so I will directly ground unconnected pins. & then MCU wakes up, will make it input -pull down also.

Amit Ashara said:

Having pull down on the unused pins gives the flexibility to connect them later. Having them to GND does not.

Agreed, although conventionally they are usually pull-ups.

There are other benefits to pull-up/dn as well. With the resistor in place rather than a direct short you can configure them as outputs as use them for debug tracing/timing.

VT, if you have the space I'd not only put in the resistors I'd put in a header to make it easy to probe or attach to the spare lines.  The header does not need to be populated but having it there makes it easy to add for later probing or additions. As well the footprint for the header makes useful probe points even if it is not populated. Headers in conjunction with multi-pack resistors is very economical. 

One of the dangers of a direct short to a power rail is the possibility of a program error that changes the pin to an output and drives to the opposite power rail.  That's never a good thing.

Robert

Hello Robert

Good suggestion on the header as well.

Regards
Amit

We MCU Users can never: be too rich, too thin, or have (enough) GPIO.   Direct connection of GPIO to either power rail most always proves "short-sighted" - sooner or later you'll NEED one or more GPIO - and their presence at a board header will prove worth its weight in gold!  

Note there will (always) be new and/or add-on projects - you're focused too much on the (limited) now - "maintaining those (presently unused) GPIO" may very well save you the time, effort, & cost of a board "re-spin."   (not to ask - how I know?...)

1. I will pull-up all unused GPIO's with 10K pull-up. Is 10K value is optimal?

2. Should all Jtag pins be pulled up by 10K? or SWCLK is to be pulled down? as in link www.support.code-red-tech.com/.../HardwareDebugConnections

I'd suggest 10K (p.u.) if pins are (unlikely) to be used and/or used w/in a (reasonably) noise-free environment. For more stressed usage 2K7 - 4K7 is our (usual) choice.

To JTAG - if your board layout on/around the JTAG pins/header is short, matched (lead length) and direct 10K should work. (again each board proves unique - you may (gradually) dial down to 4K7 as/if needed. I recognize that (another) ARM MCU vendor (which we also use) suggests pull-down for their SW_CLK - yet we've had great success w/our (past) LM3S & LX4F using 10K pull-up on both SWD & SW_CLK.

Earlier you voiced concern re: BOM cost management.  (i.e. limit components)   May I state (my belief) that such - at this time - is a BAD Idea!   Get your board to work - quickly - easily - and robustly!   Rarely (almost never) does that result from cost/part reduction at the beginning!   You need to gain experience - you can "never" fully anticipate all of the changes & expansions which await!   (and the better your product/project does - the greater will be those changes!)

Pulling up those (unused) GPIO is step 1 - yet as poster Robert advised - route them to board headers for easy attachment.  (you do NOT want to tack-solder flying leads - Never!)  (can you say, "Amateur Hour?")

Hi,

I have connected all JTAG pins with 4.7K pull up as in attached schematic.

Also will connect unused pins with 4.7K pull-up, & make 5 connections out it to header.

Design1.pdf

Hello cb1

And I did not hear it either

Regards
Amit

I swear ... Amit - there's gotta be a cb1 impersonator. Never/ever would this reporter cause/broadcast such blasphemy.

(and really, how hard is it to "hack" cb123? I'm quickly adding a 4th digit - not to guess...)

Now pounding away @ giant's design lab I can "id" your GREAT Adapter Board as, "ADA2-A" (20 pin to 10 pin ARM standard and includes Reset Switch - best we've found!)

I agree with cb1, use one of the standard JTAG connectors. ARM's reference is

infocenter.arm.com/.../cortex_debug_connectors.pdf
Assuming that the currently untied pins will be attached to circuits when you finish the schematic, the pulllups on the spares are fine. I would, however, add power and ground pins to your header. If you use the pins for profiling/debugging the ground pin is very useful. If you use as an expansion header then you need to get power and ground from somewhere. If there are going to be high speed signals on the connector then following cb1's suggestion to follow the ARM connector format with grounds on one side of the connector is a good idea.

Robert

Bonjour monsieur (Robert),

Comment Allez-Vous?.. ... et merci.

Indeed adding (both) power & ground to individual headers makes them (far more) usable.   (i.e. then a single "ID" cable may power & interconnect a 2nd board.)

Our small firm prefers to (better organize) such headers - rather than, "rain every MCU GPIO pin - in "convenient layout fashion" - upon an (overly long) header!"   For example - we usually route multiple I2C, SPI and UART signals (and only these) to our (drumbeat) "Serial Header" - along w/power/gnd.   Same holds for "Parallel Port, PWM (multi-channel), and ADC.  

The (overly) long (i.e. normal) eval board headers display "No such" organizational concern/intent - and result in a hodge-podge of "interconnect cables" (some bearing just 1 or 2 signals/leads) which sprawl (ungainly) across the "fruited plain."   Indeed the vendor has "traded" their design-ease & speed - for the user's pain/suffering - yielding at best - "spaghetti interconnect."   (thank you very much...)   And then - overly optimistic "boost-less boards" ((c) 2015, cb1, all rights reserved) "save the day" by plugging into that "disorganized header mess."   (and that reorganization adds (unwanted) size & cost to the combined board array...)

We "silk-screen" label (legibly) each of our (well considered) headers - and usually - each header employs a different number of pins - so that "cable misconnect" (really) takes great effort!