Greetings Ti Forum
I want to generate a 1Hz interrupt as accurately as possible using the Tiva C Series LaunchPad, for this reason I'm attempting to use the RTC in the Hibernation Module. My objective is then to use the 32.768 kHz crystal signal as the clock source for the RTC module and use the Hibernation Module RTC match interrupt generate the required 1 Hz interrupt.
But I have some questions on how to set it up since I cannot get the necessary clarity to do so from neither the device data sheet nor the peripheral driver library user manual (I'm programming in C).
- The bit field OSCDRV in the HIBCTL register controls the oscillator drive capability of the module. Since the Launchpad schematic specifies that 24 pF capacitors are installed with the 32.768kHz crystal, this bit should be set to one.
The Data sheet says this bit is not meant to be changed once the Hibernation oscillator has started because stability is not guaranteed if changed after the oscillator is running.
But to access the Hibernation Module Registers and set the OSCDRV bit I need to first set CLK32EN doesn’t this already start the oscillator. How can I change this setting without worrying about clock stability problems?
- In the Hibernation Control Register Description (in the data sheet) there is a mention of an internal 32.768-kHz oscillator on the description of the OSCBYP (Oscillator Bypass) bit (I didn’t find any reference to it before). When I enable the clocking on the Hibernation Module (set CLK32EN) which is the clock source used for the Hibernation Module the internal oscillator or the 32.768 crystal?
because the reset at reset OSCBYP = 1 (Internal Oscillator enabled) and OSCDRV = 0 (low crystal drive)
And how can I change to the crystal source? Disabling the oscillator (OSCBYP = 0) and setting OSCRV to 1?
- In the RTC match ISR I would like to clear the interrupt and set the RTC match value to one second in the future, hopefully without losing any of the accumulated crystal cycles in the sub-second counters. But I ran into the following problem:
According to the Datasheet the RTC match interrupt takes priority over an interrupt clear. Therefore, writes to the HIBIC.RTCALT0 ( RTCALT0 bit in the hibernation interrupt clear register) do not clear the RTCALT0 bit in HIBRIS register if the values of HIBRTCM0 and HIBRTCC are equal.
Is this true for value of these two registers exclusively or does it also include the sub-second counters (since the match functionality does extend to these additional bits) ? I could insert a 1/32.768 delay on the ISR to wait for the sub-second counter not to match and then clear the interrupt and write the new match value one secon in the future but I'm not sure it will work.
The data sheet offers two suggestions on how to deal with the problem: 1) write a new value to the load register HIBRTCLD 2) disable the RTC and re-enable the RTC. The first suggestion I didn’t like because it means I lose any accumulated sub-second counts (if any). And the second option doesn’t really explain what does enabling and disabling the RTC register do, does it clear the RTC's second count value, does it stop counting but still allow me to clear the interrupt even if the second counts match?
Hope I was clear on explaining my problem and sorry for the long post but I cant get the answers I need from the data sheet, example programs or googling it. Any help is appreciated and many thanks to those who suggest answers.