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TM4C123GE6PZ: UART bit determines

Terry Deng
Intellectual 2945 points
Part Number: TM4C123GE6PZ

Do we have document to show how UART module to determine the each bit value? I know there are internal 16 or 8 clk samples for each bit, but how many samples could decide the bit value is 0 or 1?

  • 0
    Guru 117855 points
    Long ago (6years, I believe) this topic arose during an MCU seminar. (before TM4C was introduced - this was LM3S & LX4F based)
    IIRC - UART data was sampled & examined during "3" clock edges. That "bit level" receiving "2" (or all 3) "hits" was deemed, "valid."

    That "2 of 3" UART bit, sample technique was also "in play" @ several other MCU vendors - prior to the arrival of ARM... (I recall that this method was chosen as it was fairly easy for chip vendors to implement)

    Do not "bet the farm" on this reporting - detailed review of the MCU manual (may) better reveal.
  • 0
    Expert 1690 points
    Hello Terry,
    Pages 911 - 971 of the TM4C123GE6PZ.pdf expose a detailed functional map of the UART. Accessing UART's registers bit values is a bit tricky. If you be more specific maybe someone may better help on your query.
    John
  • 0
    TI__Intellectual 2945 points

    I find below picture on C2000 DSP Datasheet to describe UART how determine the each bit value. However I cannot find such information in TM4C datasheet. where I can get any document for TM4C UART bit determine information?

  • 0 in reply to Terry Deng
    Guru 26105 points

    Hi,

    Below is an excerpt from paragraph 14.3.3 of the user manual:

    When the receiver is idle (the UnRx signal is continuously 1), and the data input goes Low (a start bit has been received), the receive counter begins running and data is sampled on the eighth cycle of Baud16 or fourth cycle of Baud8 depending on the setting of the HSE bit (bit 5) in UARTCTL (described in “Transmit/Receive Logic” on page 914).

    The start bit is valid and recognized if the UnRx signal is still low on the eighth cycle of Baud16 (HSE clear) or the fourth cycle of Baud 8 (HSE set), otherwise it is ignored. After a valid start bit is detected, successive data bits are sampled on every 16th cycle of Baud16 or 8th cycle of Baud8 (that is, one bit period later) according to the programmed length of the data characters and value of the HSE bit in UARTCTL. The parity bit is then checked if parity mode is enabled. Data length and parity are defined in the UARTLCRH register.

  • 0 in reply to Petrei
    TI__Guru 72500 points
    For each sample of data, three readings are taken and the majority value is kept. In the post above, the middle sampling point is defined, and one sample is taken either side of it.
  • 0 in reply to cb1_mobile
    Guru 117855 points

    cb1_mobile said:
    UART data was sampled & examined during "3" clock edges. That "bit level" receiving "2" (or all 3) "hits" was deemed, "valid."

    Appears (some) duplication of effort.   (and response)    Quote (above) appeared w/in (very) first response to this thread...

  • 0 in reply to cb1_mobile
    TI__Guru 72500 points
    CB1,
    Just confirming that what you reported for LM3 and Terry reported for C2000 is indeed also true for TM4C.
  • 0 in reply to Bob Crosby
    Guru 117855 points

    Thank you, Bob.    My report did target LM3S & LX4F - and as we're told that (LX4F = TM4C123) - I believed my report to enjoy (some) validity...